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1. (WO2018220471) STORAGE DEVICE AND METHOD FOR OPERATING SAME
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Pub. No.: WO/2018/220471 International Application No.: PCT/IB2018/053594
Publication Date: 06.12.2018 International Filing Date: 22.05.2018
IPC:
G11C 11/4091 (2006.01) ,G11C 7/06 (2006.01) ,G11C 11/405 (2006.01) ,H01L 21/8242 (2006.01) ,H01L 27/108 (2006.01) ,H01L 29/786 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407
for memory cells of the field-effect type
409
Read-write (R-W) circuits
4091
Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
06
Sense amplifiers; Associated circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403
with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
405
with three charge-transfer gates, e.g. MOS transistors, per cell
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8242
Dynamic random access memory structures (DRAM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 神奈川県厚木市長谷398 398, Hase, Atsugi-shi, Kanagawa 2430036, JP
Inventors:
熱海知昭 ATSUMI, Tomoaki; JP
加藤清 KATO, Kiyoshi; JP
Priority Data:
2017-10978202.06.2017JP
Title (EN) STORAGE DEVICE AND METHOD FOR OPERATING SAME
(FR) DISPOSITIF DE STOCKAGE ET SON PROCÉDÉ DE FONCTIONNEMENT
(JA) 記憶装置及びその動作方法
Abstract:
(EN) Provided is a low-power-consumption storage device. The storage device has first through third transistors, first wiring, second wiring, memory cells, and a capacitive element. The first through third transistors are serially connected. High-power-source voltage is applied to the drain of the first transistor, and low-power-source voltage is applied to the source of the third transistor. The gate of the second transistor is electrically connected to the memory cells via the first wiring. The second wiring is electrically connected to the source of the second transistor and to the capacitive element. A clock signal is applied to the gate of the first transistor, and a reverse clock signal is applied to the gate of the third transistor. The first through third transistors have oxide semiconductors in channel formation regions.
(FR) L'invention concerne un périphérique de stockage à faible consommation d’énergie. Le dispositif de stockage comporte des premier à troisième transistors, un premier câblage, un second câblage, des cellules de mémoire et un élément capacitif. Les premier et troisième transistors sont connectés en série. Une tension de source de puissance élevée est appliquée au drain du premier transistor, et une tension de source de faible puissance est appliquée à la source du troisième transistor. La grille du second transistor est connectée électriquement aux cellules de mémoire par l'intermédiaire du premier câblage. Le second câblage est connecté électriquement à la source du second transistor et à l'élément capacitif. Un signal d'horloge est appliqué à la grille du premier transistor, et un signal d'horloge inverse est appliqué à la grille du troisième transistor. Les premier à troisième transistors comportent des semi-conducteurs d'oxyde dans des régions de formation de canal.
(JA) 要約書 消費電力の小さい記憶装置を提供する。 第1乃至第3のトランジスタと、 第1配線と、 第2配線と、 メモリセルと、 容量素子を有する記憶装 置である。 第1乃至第3トランジスタは直列に接続されている。 第1トランジスタのドレインは高電 源電圧が与えられ、 第3トランジスタのソースは低電源電圧が与えられる。 第2トランジスタのゲー トは第1配線を介してメモリセルに電気的に接続される。 第2配線は、 第2トランジスタのソースお よび容量素子に電気的に接続される。 第1トランジスタのゲートはクロック信号が与えられ、 第3ト ランジスタのゲートは反転クロック信号が与えられる。第1乃至第3トランジスタはチャネル形成領 域に酸化物半導体を有する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)