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1. (WO2018220359) HYSTERETIC COMPARATOR BASED TIME ENCODING MODULATION

Pub. No.:    WO/2018/220359    International Application No.:    PCT/GB2018/051461
Publication Date: Fri Dec 07 00:59:59 CET 2018 International Filing Date: Thu May 31 01:59:59 CEST 2018
IPC: H03M 1/18
H03M 1/50
Applicants: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LIMITED
Inventors: LESSO, John Paul
SINGLETON, David Paul
Title: HYSTERETIC COMPARATOR BASED TIME ENCODING MODULATION
Abstract:
This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse- width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN).