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1. (WO2018220275) SEMICONDUCTOR APPARATUS
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Pub. No.: WO/2018/220275 International Application No.: PCT/FI2018/050404
Publication Date: 06.12.2018 International Filing Date: 28.05.2018
IPC:
H01L 27/01 (2006.01) ,H01L 21/762 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
01
comprising only passive thin-film or thick-film elements formed on a common insulating substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
Applicants:
TEKNOLOGIAN TUTKIMUSKESKUS VTT OY [FI/FI]; Vuorimiehentie 3 02150 Espoo, FI
Inventors:
VILJANEN, Heikki; FI
RANTAKARI, Pekka; FI
VÄHÄ-HEIKKILÄ, Tauno; FI
TUOVINEN, Esa; FI
Agent:
ESPATENT OY; Kaivokatu 10 D 00100 Helsinki, FI
Priority Data:
2017548029.05.2017FI
Title (EN) SEMICONDUCTOR APPARATUS
(FR) APPAREIL À SEMICONDUCTEUR
Abstract:
(EN) A semiconductor apparatus (200, 300) comprising a silicon substrate layer (210) at least portion of which is doped with dopants of a conductivity type; and at least one insulator layer (220) formed above the silicon substrate layer (210), wherein the at least one insulator layer (220) and the dopants of the silicon substrate layer (210) have opposite electric charges.
(FR) L'invention concerne un appareil à semi-conducteur (200, 300) comprenant une couche de substrat de silicium (210) dont au moins une partie est dopée avec des dopants d'un type de conductivité; et au moins une couche d'isolation (220) formée au-dessus de la couche de substrat de silicium (210), l'au moins une couche d'isolation (220) et les dopants de la couche de substrat de silicium (210) ayant des charges électriques opposées.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)