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1. (WO2018219067) ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, DISPLAY DEVICE AND DRIVING METHOD THEREFOR
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Pub. No.: WO/2018/219067 International Application No.: PCT/CN2018/084243
Publication Date: 06.12.2018 International Filing Date: 24.04.2018
IPC:
G02F 1/1333 (2006.01)
[IPC code unknown for G02F 1/1333]
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
合肥京东方光电科技有限公司 HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国安徽省合肥市 铜陵北路2177号 No.2177 Tonglingbei Road Hefei, Anhui 230012, CN
Inventors:
绪浩舒 XU, Haoshu; CN
宫奎 GONG, Kui; CN
崔显西 CUI, Xianxi; CN
Agent:
北京市柳沈律师事务所 LIU, SHEN & ASSOCIATES; 中国北京市 海淀区彩和坊路10号1号楼10层 10th Floor, Building 1, 10 Caihefang Road, Haidian District Beijing 100080, CN
Priority Data:
201710407555.102.06.2017CN
Title (EN) ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, DISPLAY DEVICE AND DRIVING METHOD THEREFOR
(FR) SUBSTRAT EN RÉSEAU ET SON PROCÉDÉ DE FABRICATION, DISPOSITIF D'AFFICHAGE ET SON PROCÉDÉ DE COMMANDE
(ZH) 阵列基板及其制作方法、显示装置及其驱动方法
Abstract:
(EN) An array substrate and a manufacturing method therefor, a display device and a driving method therefor. The array substrate (111) comprises: a first thin film transistor (30), a second thin film transistor (31) and a pixel electrode (40), the pixel electrode (40) being electrically connected to the first thin film transistor (30) and the second thin film transistor (31), one of the first thin film transistor (30) and the second thin film transistor (31) being an n-type thin film transistor, and another one being a p-type thin film transistor. The array substrate (111) and the manufacturing method therefor, the display device and the driving method therefor can reduce the influence of turn off current on pixels, thereby avoiding the occurrence of related defects.
(FR) L'invention concerne un substrat en réseau et son procédé de fabrication, un dispositif d'affichage et son procédé de commande. Le substrat en réseau (111) comprend : un premier transistor en couches minces (30), un second transistor en couches minces (31) et une électrode de pixel (40), l'électrode de pixel (40) étant électriquement connectée au premier transistor en couches minces (30) et au second transistor en couches minces (31), l'un du premier transistor en couches minces (30) et du second transistor en couches minces (31) étant un transistor en couches minces de type n et un autre étant un transistor en couches minces de type p. Le substrat en réseau (111) et son procédé de fabrication, le dispositif d'affichage et son procédé de commande peuvent réduire l'influence d'un courant d'arrêt sur des pixels et ainsi éviter l'apparition de défauts apparentés.
(ZH) 一种阵列基板及其制作方法、显示装置及其驱动方法。阵列基板(111)包括:包括:第一薄膜晶体管(30),第二薄膜晶体管(31)和像素电极(40),像素电极(40)与第一薄膜晶体管(30)和第二薄膜晶体管(31)电连接,第一薄膜晶体管(30)和第二薄膜晶体管(31)之一为N型薄膜晶体管,另一个为P型薄膜晶体管。阵列基板(111)及其制作方法、显示装置及其驱动方法可以降低关断电流对像素的影响,从而避免相关不良的发生。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)