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1. (WO2018218987) DISPLAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING DISPLAY SUBSTRATE
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Pub. No.: WO/2018/218987 International Application No.: PCT/CN2018/075081
Publication Date: 06.12.2018 International Filing Date: 02.02.2018
IPC:
H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District, Beijing 100015, CN
Inventors:
ZHANG, Feng; CN
LV, Zhijun; CN
LIU, Wenqu; CN
DONG, Liwen; CN
ZHANG, Shizheng; CN
DANG, Ning; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; CHEN, Yuan 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District, Beijing 100005, CN
Priority Data:
201710417593.502.06.2017CN
Title (EN) DISPLAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING DISPLAY SUBSTRATE
(FR) SUBSTRAT D'AFFICHAGE, APPAREIL D'AFFICHAGE ET PROCÉDÉ DE FABRICATION DE SUBSTRAT D'AFFICHAGE
Abstract:
(EN) A display substrate has a base substrate (1); an insulating layer (2) on the base substrate (1); and an electrode layer (3) on a side of the insulating layer (2) distal to the base substrate (1) and having a plurality of electrode blocks (33). The insulating layer (2) has a first side (S1) distal to the base substrate (1) and a second side (S2) opposite to the first side (S1) and proximal to the base substrate (1). Each of the plurality of electrode blocks (33) has a third side (S3) distal to the base substrate (1) and a fourth side (S4) opposite to the third side (S3) and proximal to the base substrate (1). The first side (S1) of the insulating layer (2) in the inter-electrode block region (31) has a first height (L1) relative to a surface of the base substrate (1) greater than a second height (L2) of the fourth side (S4) of an adjacent electrode of the plurality of electrode blocks (33) relative to the surface of the base substrate (1).
(FR) L'invention concerne un substrat d'affichage ayant un substrat de base (1); une couche d'isolation (2) sur le substrat de base (1); et une couche d'électrode (3) sur un côté de la couche isolation (2) distal par rapport au substrat de base (1) et ayant une pluralité de blocs d'électrode (33). La couche d'isolation (2) a un premier côté (S1) distal par rapport au substrat de base (1) et un second côté (S2) opposé au premier côté (S1) et proximal au substrat de base (1). Chacun de la pluralité de blocs d'électrode (33) a un troisième côté (S3) distal par rapport au substrat de base (1) et un quatrième côté (S4) opposé au troisième côté (S3) et proximal au substrat de base (1). Le premier côté (S1) de la couche d'isolation (2) dans la région de bloc inter-électrodes (31) a une première hauteur (L1) par rapport à une surface du substrat de base (1) supérieure à une seconde hauteur (L2) du quatrième côté (S4) d'une électrode adjacente de la pluralité de blocs d'électrode (33) par rapport à la surface du substrat de base (1).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)