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1. (WO2018205528) THIN-FILM TRANSISTOR AND PREPARATION METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY DEVICE
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Pub. No.: WO/2018/205528 International Application No.: PCT/CN2017/110441
Publication Date: 15.11.2018 International Filing Date: 10.11.2017
IPC:
H01L 21/336 (2006.01) ,H01L 29/786 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No. 10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
合肥京东方光电科技有限公司 HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国安徽省合肥市 铜陵北路2177号 No. 2177 Tonglingbei Road Hefei, Anhui 230012, CN
Inventors:
宫奎 GONG, Kui; CN
段献学 DUAN, Xianxue; CN
李纪龙 LI, Jilong; CN
Agent:
北京同达信恒知识产权代理有限公司 TDIP & PARTNERS; 中国北京市海淀区宝盛南路1号院20号楼8层101-01 101-01, 8/F, Building 20, No.1 Baosheng South Road Haidian District Beijing 100192, CN
Priority Data:
201710318885.308.05.2017CN
Title (EN) THIN-FILM TRANSISTOR AND PREPARATION METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY DEVICE
(FR) TRANSISTOR EN COUCHES MINCES ET SON PROCÉDÉ DE PRÉPARATION, SUBSTRAT MATRICIEL ET DISPOSITIF D'AFFICHAGE
(ZH) 薄膜晶体管及其制备方法、阵列基板和显示装置
Abstract:
(EN) A thin-film transistor and preparation method therefor, an array substrate, and a display device. The method comprises: preparing an etch-resistant layer pattern (301) on an active layer (204), wherein a conducting medium is doped in the etch-resistant layer pattern (301); etching the region in the active layer (204) that is not covered by the etch-resistant layer pattern (301) to form an active layer pattern (401), and retaining the etch-resistant layer pattern (301); and preparing a source (901) and a drain (902) of a thin-film transistor. Good electrical contact regions are formed between the source and the active layer and between the drain and the active layer because the conducting medium with low resistivity is doped in the etch-resistant layer pattern.
(FR) La présente invention concerne un transistor en couches minces et son procédé de préparation, un substrat matriciel et un dispositif d’affichage. Le procédé consiste : à préparer un motif de couche résistante à la gravure (301) sur une couche active (204), un milieu conducteur étant dopé dans le motif de couche résistante à la gravure (301) ; à graver la région dans la couche active (204) qui n'est pas recouverte du motif de couche résistante à la gravure (301) de manière à former un motif de couche active (401), et à conserver le motif de couche résistante à la gravure (301) ; et à préparer une source (901) et un drain (902) d'un transistor en couches minces. Par dopage du milieu conducteur à faible résistivité dans le motif de couche résistante à la gravure, de bonnes régions de contact électrique formées entre la source et la couche active et entre le drain et la couche active peuvent être obtenues.
(ZH) 一种薄膜晶体管及其制备方法、阵列基板和显示装置。方法包括:在有源层(204)上制备抗刻蚀层图案(301),其中抗刻蚀层图案(301)中掺杂有导电介质;刻蚀掉有源层(204)中未被抗刻蚀层图案(301)覆盖的区域形成有源层图案(401),并保留抗刻蚀层图案(301);制备薄膜晶体管的源极(901)和漏极(902)。由于抗刻蚀层图案掺杂有电阻率较低的导电介质,使得源极与有源层和漏极与有源层之间形成良好的电接触区域。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)