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1. (WO2018204898) FAST BINARY COUNTERS BASED ON SYMMETRIC STACKING AND METHODS FOR SAME
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Pub. No.: WO/2018/204898 International Application No.: PCT/US2018/031268
Publication Date: 08.11.2018 International Filing Date: 04.05.2018
IPC:
G06F 12/02 (2006.01) ,G06F 7/48 (2006.01) ,G06F 7/50 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
50
Adding; Subtracting
Applicants:
THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK [US/US]; Technology Transfer, University At Buffalo UB Commons, 520 Lee Entrance, Suite 109 Buffalo, NY 14228-2567, US
Inventors:
FRITZ, Christopher; US
FAM, Adly, T.; US
Agent:
CUTAIA, Alfonzo, I.; US
ROMAN, Paul, J.; US
WATT, Rachel, S.; US
LOPINSKI, John, D.; US
KADLE, Ranjana; US
Priority Data:
62/501,73104.05.2017US
Title (EN) FAST BINARY COUNTERS BASED ON SYMMETRIC STACKING AND METHODS FOR SAME
(FR) COMPTEURS BINAIRES RAPIDES BASÉS SUR UN EMPILEMENT SYMÉTRIQUE ET PROCÉDÉS ASSOCIÉS
Abstract:
(EN) In this paper, binary stackers and counters are presented. In an embodiment, a counter uses 3-bit stacking circuits which group the T bits together, followed by a symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted to binary counts, producing 6:3 and 7:3 Counter circuits with no XOR gates on the critical path. This avoidance of XOR gates results in faster designs with efficient power and area utilization. In VLSI simulations, the presently-disclosed counters were 30% faster and at consumed at least 20% less power than existing parallel counters. Additionally, using the presently-disclosed counter in existing Counter Based Wallace tree multiplier architectures reduces latency and improves efficiency in terms of power-delay product for 64-bit and 128-bit multipliers.
(FR) La présente invention concerne des empileurs binaires et des compteurs binaires. Selon un mode de réalisation, un compteur utilise des circuits d'empilement de 3 bits qui regroupent les T bits ensemble, suivi d'un procédé symétrique pour combiner des paires d'empilements de 3 bits en empilements de 6 bits. Les empilements de bits sont ensuite convertis en nombres binaires, produisant 6:3 et 7:3 circuits de compteur sans portes OU exclusif sur le trajet essentiel. Le fait de ne pas utiliser de portes OU exclusif a pour résultat des conceptions plus rapides avec une utilisation efficace de la puissance et de la superficie. Dans des simulations d'intégration à très grande échelle, les compteurs selon la présente invention étaient de 30 % plus rapides et consommaient au moins 20 % d'énergie en moins que les compteurs parallèles existants. De plus, l'utilisation du compteur selon la présente invention dans des architectures existantes de multiplicateur à arbre de Wallace basé sur un compteur réduit la latence et améliore l'efficacité en termes de produit de retard de puissance pour des multiplicateurs de 64 bits et de 128 bits.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)