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1. (WO2018204512) INPUT IMPEDANCE BIASING

Pub. No.:    WO/2018/204512    International Application No.:    PCT/US2018/030684
Publication Date: Fri Nov 09 00:59:59 CET 2018 International Filing Date: Thu May 03 01:59:59 CEST 2018
IPC: H03F 3/185
Applicants: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
SARAF, Vivek
THOMSEN, Axel
KUMMARAGUNTLA, Ravi
TUCKER, John, Christopher
Inventors: SARAF, Vivek
THOMSEN, Axel
KUMMARAGUNTLA, Ravi
TUCKER, John, Christopher
Title: INPUT IMPEDANCE BIASING
Abstract:
Input impedance biasing may be improved with an ultra-high-input-impedance biasing circuit having low temperature variation. The impedance biasing circuit may include a first transistor coupled to a first power supply and a second transistor coupled to a second power supply. A gate of the first transistor may be coupled to a gate of the second transistor at an intermediate bias node. The first transistor and the second transistor may provide a selected DC impedance at the intermediate bias node. The impedance may be used to provide low-pass and or high-pass filtering of audio signals and/or noise.