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1. (WO2018204500) MANUFACTURING METHODS TO REDUCE SURFACE PARTICLE IMPURITIES AFTER A PLASMA PROCESS
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Pub. No.: WO/2018/204500 International Application No.: PCT/US2018/030660
Publication Date: 08.11.2018 International Filing Date: 02.05.2018
IPC:
H01L 21/3065 (2006.01) ,H01L 21/02 (2006.01) ,H01L 21/311 (2006.01) ,H01L 21/3213 (2006.01) ,H01L 21/67 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Applicants:
TOKYO ELECTRON LIMITED [JP/JP]; Akasaka Biz Tower 3-1 Akasaka 5-chome Minato-ku, Tokyo 107-6325, JP
TOKYO ELECTRON U.S. HOLDINGS, INC. [US/US]; 2400 Grove Boulevard Austin, Texas 78741, US (JP)
Inventors:
MARION, Jason; US
YOSHIDA, Yusuke; US
BATHRICK, Brendan; US
VORONIN, Sergey; US
RANJAN, Alok; US
Agent:
MADRIAGA, Manuel B.; US
Priority Data:
62/500,26102.05.2017US
62/552,10630.08.2017US
Title (EN) MANUFACTURING METHODS TO REDUCE SURFACE PARTICLE IMPURITIES AFTER A PLASMA PROCESS
(FR) PROCÉDÉS DE FABRICATION POUR RÉDUIRE DES IMPURETÉS DE PARTICULES DE SURFACE APRÈS UN TRAITEMENT AU PLASMA
Abstract:
(EN) Manufacturing methods are disclosed to reduce surface particle impurities after a plasma process (e.g., etch, deposition, etc.) by repelling particles trapped within particle wells to reduce surface particle impurities on microelectronic workpieces after termination of the plasma process. Rather than turn off pressure and source power at the termination of the plasma process, the disclosed embodiments first enter a sequence to adjust process parameters to repel particles in a particle well in order to reduce or eliminate the particle well prior to terminating the plasma process. During this particle repel sequence, certain disclosed embodiments adjust parameters to maintain an electrostatic field above the surface of the wafer utilizing low plasma density and ion energy conditions that help to repel particles from the microelectronic workpiece. The disclosed methods allow for the particle well to be exhausted well prior to the collapse of electrostatic forces when the plasma process is terminated.
(FR) L'invention concerne des procédés de fabrication pour réduire des impuretés de particules de surface après un traitement au plasma (par exemple, gravure, dépôt, et analogues.) en repoussant des particules piégées dans les puits de particules pour réduire les impuretés de particules de surface sur des pièces micro-électroniques après l'achèvement du traitement au plasma. Au lieu d'interrompre la pression et la puissance de source à la fin du traitement au plasma, les modes de réalisation selon l'invention entrent d'abord une séquence pour ajuster des paramètres de traitement pour repousser des particules dans un puits de particules afin de réduire ou d'éliminer le puits de particules avant l'achèvement du traitement au plasma. Lors de cette séquence de répulsion de particules, certains modes de réalisation selon la présente invention ajustent des paramètres pour maintenir un champ électrostatique au-dessus de la surface de la tranche au moyen d'une faible densité de plasma et des conditions d'énergie ionique qui aident à repousser les particules depuis la pièce microélectronique. Les procédés selon la présente invention permettent une bonne évacuation du puits de particules avant l'effondrement des forces électrostatiques lorsque le traitement au plasma est terminé.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)