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1. (WO2018204487) HIGH SPEED SEMICONDUCTOR CHIP STACK
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Pub. No.: WO/2018/204487 International Application No.: PCT/US2018/030634
Publication Date: 08.11.2018 International Filing Date: 02.05.2018
IPC:
H01G 4/12 (2006.01) ,H01G 4/005 (2006.01) ,H01G 4/248 (2006.01) ,H01G 4/30 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
002
Details
018
Dielectrics
06
Solid dielectrics
08
Inorganic dielectrics
12
Ceramic dielectrics
[IPC code unknown for H01G 4/05]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
002
Details
228
Terminals
248
the terminals embracing or surrounding the capacitive element, e.g. caps
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
30
Stacked capacitors
Applicants:
DE ROCHEMONT, L. Pierre [US/US]; US
Inventors:
DE ROCHEMONT, L. Pierre; US
Agent:
GOMES, David W.; US
CHACLAS, George N.; US
CHOW, Stephen Y.; US
CLARKE, Daniel; US
COHEN, Jerry; US
COWLES, Christopher R.; US
EMMONS, Richard B.; US
FOLEY, Shawn P.; US
GOLDMAN, Gabriel; US
SORKIN, Paul D.; US
HASAN, Shahid; US
JOBSE, Bruce D.; US
LOPEZ, Orlando; US
MARAIA, Joseph M.; US
MCGRATH, Daniel; US
MOORE, Ronda P.; US
QUINN, Joseph P.; US
SCHEPPER, Marlo; US
SERIO, John C.; US
MILLS, Steven M.; US
SUSAN, Janine M.; US
Priority Data:
62/500,17702.05.2017US
62/582,18206.11.2017US
Title (EN) HIGH SPEED SEMICONDUCTOR CHIP STACK
(FR) EMPILEMENT DE PUCES SEMI-CONDUCTRICES À GRANDE VITESSE
Abstract:
(EN) The present invention ultra-low loss high energy density dielectric layers having femtosecond (10-15 sec) polarization response times within a chip stack assembly to extend impedance-matched electrical lengths and mitigate ringing within the chip stack to bring the operational clock speed of the stacked system closer to the intrinsic clock speed(s) of the semiconductor die bonded within chip stack.
(FR) Les couches diélectriques à haute densité d'énergie à faible perte selon la présente invention présentent des temps de réponse de polarisation de l'ordre de la femtoseconde (10-15 s) à l'intérieur d'un ensemble empilement de puces pour étendre des longueurs électriques adaptées à l'impédance et atténuer la sonnerie dans l'empilement de puces afin d'amener la vitesse d'horloge opérationnelle du système empilé à se rapprocher de la ou des vitesses d'horloge intrinsèques de la puce semi-conductrice liée à l'empilement de puces.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)