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1. (WO2018204464) MEMORY TRACKING USING COPY-BACK CACHE FOR 1:1 DEVICE REDUNDANCY

Pub. No.:    WO/2018/204464    International Application No.:    PCT/US2018/030599
Publication Date: Fri Nov 09 00:59:59 CET 2018 International Filing Date: Thu May 03 01:59:59 CEST 2018
IPC: G06F 12/0806
G05B 23/02
G06F 3/06
G06F 11/20
G06F 12/0811
Applicants: HONEYWELL INTERNATIONAL INC.
Inventors: MCLAUGHLIN, Paul, F.
MASSEY, William, Russell, Jr.
DRAYTON, Gary
CHERNOGUZOV, Alexander
Title: MEMORY TRACKING USING COPY-BACK CACHE FOR 1:1 DEVICE REDUNDANCY
Abstract:
A redundant process controller arrangement (160) includes a primary controller (138a) and parallel connected secondary controller (138b) each coupled to actuators (113) and sensors (112) coupled to processing equipment (114). The primary and secondary controllers include a main writable memory (120a, 120b) including a cache data control algorithm (120a3, 120b3), central processing unit (CPU) (125a, 125b) with cache memory including cache not supporting write-thru, tracker logic (130a, 130b) coupled to a control cycle database in a tracked memory region (120a1, 120b1) and to a primary tracking buffer (120a2). A redundancy link (150) is between the CPUs for passing tracked changes. The algorithm implements memory tracking using copy-back including the primary tracker logic each cycle writing tracked changes into the primary tracking buffer, and at cycle end, transferring tracked changes from the primary tracking buffer to the secondary controller over the redundancy link, and writing tracked changes to the secondary control database.