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1. (WO2018204193) DESIGN LAYOUT PATTERN PROXIMITY CORRECTION THROUGH EDGE PLACEMENT ERROR PREDICTION

Pub. No.:    WO/2018/204193    International Application No.:    PCT/US2018/029874
Publication Date: Fri Nov 09 00:59:59 CET 2018 International Filing Date: Sat Apr 28 01:59:59 CEST 2018
IPC: G03F 7/20
G03F 1/72
Applicants: LAM RESEARCH CORPORATION
Inventors: TETIKER, Mehmet Derya
SRIRAMAN, Saravanapriyan
BAILEY, Andrew D. III
WISE, Richard
Title: DESIGN LAYOUT PATTERN PROXIMITY CORRECTION THROUGH EDGE PLACEMENT ERROR PREDICTION
Abstract:
Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.