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1. (WO2018204181) STANDARD CELL LAYOUT ARCHITECTURES AND DRAWING STYLES FOR 5NM AND BEYOND

Pub. No.:    WO/2018/204181    International Application No.:    PCT/US2018/029767
Publication Date: Fri Nov 09 00:59:59 CET 2018 International Filing Date: Sat Apr 28 01:59:59 CEST 2018
IPC: H01L 27/02
H01L 23/528
G06F 17/50
H01L 21/8234
H01L 21/8238
Applicants: ADVANCED MICRO DEVICES, INC.
Inventors: SCHULTZ, Richard T.
Title: STANDARD CELL LAYOUT ARCHITECTURES AND DRAWING STYLES FOR 5NM AND BEYOND
Abstract:
A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap (522A, 522B, 522C) as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.