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1. (WO2018204115) INTEGRATED CIRCUIT (IC) PACKAGE AND PACKAGE SUBSTRATE COMPRISING STACKED VIAS

Pub. No.:    WO/2018/204115    International Application No.:    PCT/US2018/028903
Publication Date: Fri Nov 09 00:59:59 CET 2018 International Filing Date: Tue Apr 24 01:59:59 CEST 2018
IPC: H01L 23/498
H01L 21/48
Applicants: QUALCOMM INCORPORATED
Inventors: KANG, Kuiwon
JOMAA, Houssam
ROUHANA, Layal
CHOI, Seongryul
Title: INTEGRATED CIRCUIT (IC) PACKAGE AND PACKAGE SUBSTRATE COMPRISING STACKED VIAS
Abstract:
A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.