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1. (WO2018203754) CACHE COHERENT NODE CONTROLLER FOR SCALE-UP SHARED MEMORY SYSTEMS
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Pub. No.: WO/2018/203754 International Application No.: PCT/NO2018/050115
Publication Date: 08.11.2018 International Filing Date: 30.04.2018
IPC:
G06F 12/0813 (2016.01) ,G06F 15/173 (2006.01) ,G06F 12/0815 (2016.01) ,G06F 12/0817 (2016.01) ,G06F 13/40 (2006.01)
[IPC code unknown for G06F 12/0813]
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
16
Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
163
Interprocessor communication
173
using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
[IPC code unknown for G06F 12/0815][IPC code unknown for G06F 12/0817]
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
40
Bus structure
Applicants:
NUMASCALE AS [NO/NO]; Innspurten 15 0663 Oslo, NO
Inventors:
RUSTAD, Einar; NO
SIMONSEN, Helge; NO
PERSVOLD, Steffen; NO
DEBNATH, Goutam; US
MOEN, Thomas; NO
Agent:
BRYN AARFLOT AS; P.O. Box 449 Sentrum 0104 OSLO, NO
Priority Data:
2017071902.05.2017NO
Title (EN) CACHE COHERENT NODE CONTROLLER FOR SCALE-UP SHARED MEMORY SYSTEMS
(FR) CONTRÔLEUR DE NŒUD COHÉRENT DE MÉMOIRE CACHE POUR SYSTÈMES DE MÉMOIRE PARTAGÉE À ÉVOLUTIVITÉ VERTICALE
Abstract:
(EN) The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.
(FR) La présente invention concerne des contrôleurs de nœud cohérent de mémoire cache pour des systèmes de mémoire partagée à évolutivité verticale. La présente invention concerne en particulier un système informatique comprenant au moins un premier groupe de modules d'UC connectés à au moins un premier contrôleur de nœud FPGA conçu pour exécuter des transactions directement ou par l'intermédiaire d'un premier commutateur d'interconnexion à destination d'au moins un second contrôleur de nœud FPGA connecté à un second groupe de modules d'UC exécutant une seule instance d'un système d'exploitation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)