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1. (WO2018203246) ELECTRO-OPTICAL DEVICE WITH III- V GAIN MATERIALS AND INTEGRATED HEAT SINK
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Pub. No.: WO/2018/203246 International Application No.: PCT/IB2018/053033
Publication Date: 08.11.2018 International Filing Date: 02.05.2018
IPC:
H01L 33/64 (2010.01) ,H01S 5/323 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
64
Heat extraction or cooling elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
S
DEVICES USING STIMULATED EMISSION
5
Semiconductor lasers
30
Structure or shape of the active region; Materials used for the active region
32
comprising PN junctions, e.g. hetero- or double- hetero-structures
323
in AIIIBV compounds, e.g. AlGaAs-laser
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, New York 10504, US
IBM UNITED KINGDOM LIMITED [GB/GB]; PO Box 41, North Harbour Portsmouth Hampshire PO6 3AU, GB (MG)
IBM (CHINA) INVESTMENT COMPANY LIMITED [CN/CN]; 25/F, Pangu Plaza No.27, Central North 4th Ring Road, Chaoyang District, Beijing 100101, CN (MG)
Inventors:
CAER, Charles; CH
HAHN, Herwig; CH
Agent:
GRAHAM, Timothy; GB
Priority Data:
15/587,75405.05.2017US
15/804,71606.11.2017US
Title (EN) ELECTRO-OPTICAL DEVICE WITH III- V GAIN MATERIALS AND INTEGRATED HEAT SINK
(FR) DISPOSITIF ÉLECTRO-OPTIQUE À MATÉRIAUX DE GAIN III-V ET DISSIPATEUR THERMIQUE INTÉGRÉ
Abstract:
(EN) An electro-optical device having two wafer components and a device fabrication method. A first wafer component includes a silicon substrate and a cladding layer on top thereof. The cladding layer comprises a cavity formed therein, wherein the cavity is filled with an electrically insulating thermal spreader, which has a thermal conductivity larger than that of the cladding layer. The second wafer component comprises a stack of III - V semiconductor gain materials, designed for optical amplification of a given radiation. The second wafer component is bonded to the first wafer component, such that the stack of III - V semiconductor gain materials is in thermal communication with the thermal spreader. In addition, the thermal spreader has a refractive index that is lower than each of the refractive index of the silicon substrate and an average refractive index of the stack of III - V semiconductor gain materials for said given radiation.
(FR) L'invention concerne un dispositif électro-optique ayant deux composants de tranche et un procédé de fabrication du dispositif. Un premier composant de tranche comprend un substrat de silicium et une couche de placage sur le dessus de celui-ci. La couche de gainage comprend une cavité formée à l'intérieur, la cavité étant remplie d'un dissipateur thermique électroisolant, qui a une conductivité thermique supérieure à celle de la couche de gainage. Le second composant de tranche comprend un empilement de matériaux de gain semi-conducteur III-V, conçu pour l'amplification optique d'un rayonnement donné. Le second composant de tranche est lié au premier composant de tranche, de telle sorte que l'empilement de matériaux de gain semi-conducteur III-V est en communication thermique avec le diffuseur thermique. De plus, le diffuseur thermique a un indice de réfraction qui est inférieur à chacun de l'indice de réfraction du substrat de silicium et de l'indice de réfraction moyen de l'empilement de matériaux de gain semi-conducteur III-V pour ledit rayonnement donné.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)