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1. (WO2018203149) STRONGARM LATCH COMPARATOR AND METHOD
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Pub. No.: WO/2018/203149 International Application No.: PCT/IB2018/050290
Publication Date: 08.11.2018 International Filing Date: 17.01.2018
IPC:
H03K 5/24 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
5
Manipulating pulses not covered by one of the other main groups in this subclass
22
Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
24
the characteristic being amplitude
Applicants:
KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY [SA/SA]; 4700 King Abdullah University of Science and Technology Thuwal 23955-6900, SA
Inventors:
ALMANSOURI, Abdullah Saud; SA
ALTURKI, Abdullah Turki; SA
AL-ATTAR, Talal; SA
Priority Data:
62/500,13602.05.2017US
Title (EN) STRONGARM LATCH COMPARATOR AND METHOD
(FR) COMPARATEUR DE VERROUILLAGE DE COFFRE-FORT ET PROCÉDÉ
Abstract:
(EN) A StrongARM latch comparator (500) includes first and second p-type metal- oxide-semiconductor, PMOS, cross-coupled transistors (T1, T2); third and fourth n- type metal-oxide-semiconductor, NMOS, cross-coupled transistors (T3, T4), wherein the first PMOS cross-coupled transistor (T1) has a gate electrically coupled to a gate of the third NMOS cross-coupled transistor (T3) and the second PMOS cross- coupled transistor (T2) has a gate electrically coupled to a gate of the fourth NMOS cross-coupled transistor (T4); and fifth and sixth input transistors (T5, T6). The fifth input transistor (T5) is electrically connected between the first PMOS cross-coupled transistor (T1) and the third NMOS cross-coupled transistor (T3), and the sixth input transistor (T6) is electrically connected between the second PMOS cross-coupled transistor (T2) and the fourth NMOS cross-coupled transistor (T4).
(FR) Un comparateur de verrouillage de coffre-fort (500) comprend des premier et deuxième transistors à couplage transversal métal-oxyde-semi-conducteur à canal p, PMOS (T1, T2) ; des troisième et quatrième transistors à couplage transversal métal-oxyde-semi-conducteur à canal n, NMOS (T3, T4), le premier transistor à couplage transversal PMOS (T1) a une grille couplée électriquement à une grille du troisième transistor à couplage transversal NMOS (T3) et le deuxième transistor à couplage transversal PMOS (T2) a une grille couplée électriquement à une grille du quatrième transistor à couplage transversal NMOS (T4) ; et des cinquième et sixième transistors d'entrée (T5, T6). Le cinquième transistor d'entrée (T5) est connecté électriquement entre le premier transistor à couplage transversal PMOS (T1) et le troisième transistor à couplage transversal NMOS (T3), et le sixième transistor d'entrée (T6) est connecté électriquement entre le deuxième transistor à couplage transversal PMOS (T2) et le quatrième transistor à couplage transversal NMOS (T4).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)