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1. (WO2018201758) THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, DISPLAY DEVICE
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Pub. No.: WO/2018/201758 International Application No.: PCT/CN2018/073806
Publication Date: 08.11.2018 International Filing Date: 23.01.2018
IPC:
H01L 29/786 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd. Chaoyang District Beijing 100015, CN
Inventors:
王国英 WANG, Guoying; CN
宋振 SONG, Zhen; CN
Agent:
北京三高永信知识产权代理有限责任公司 BEIJING SAN GAO YONG XIN INTELLECTUAL PROPERTY AGENCY CO., LTD.; 中国北京市 海淀区学院路蓟门里和景园A座1单元102室 A-1-102,He Jing Yuan, Ji Men Li, Xueyuan Road Haidian District Beijing 100088, CN
Priority Data:
201710309534.604.05.2017CN
Title (EN) THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, DISPLAY DEVICE
(FR) TRANSISTOR À COUCHES MINCES ET SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF D’AFFICHAGE
(ZH) 一种薄膜晶体管及其制造方法、显示装置
Abstract:
(EN) A thin film transistor and a manufacturing method therefor, and a display device, belonging to the field of semiconductors. The thin film transistor comprises a first active layer (21), a source electrode (31), a drain electrode (32), a gate electrode (33) and a second active layer (22); the source electrode (31), the drain electrode (32), and the gate electrode (33) are provided apart from one another on the first active layer (21); the gate electrode (33) is provided between the source electrode (31) and the drain electrode (32); the second active layer (22) is provided on the gate electrode (33), the source electrode (31) and the drain electrode (32); both the source electrode (31) and the drain electrode (32) are connected to the first active layer (21) and the second active layer (22); and the gate electrode (33) is respectively insulated from the first active layer (21), the second active electrode (22), the source electrode (31) and the drain electrode (32); when a voltage is applied to the gate electrode (33), the source electrode (31) and the drain electrode (32) can be connected by means of the first active layer (21), and the source electrode (31) and the drain electrode (32) can also be connected by means of the second active layer (22); as both the source electrode (31) and the drain electrode (32) can be connected simultaneously by means of the first active layer (21) and the second active layer (22) when the thin film transistor is connected, a larger current can flow between the source electrode (31) and the drain electrode (32), so as to increase the on-state current of the thin film transistor.
(FR) L'invention concerne un transistor à couches minces et son procédé de fabrication, et un dispositif d'affichage, appartenant au domaine des semi-conducteurs. Le transistor à couches minces comprend une première couche active (21), une électrode de source (31), une électrode de drain (32), une électrode de grille (33) et une seconde couche active (22) ; l'électrode de source (31), l'électrode de drain (32) et l'électrode de grille (33) sont espacées l'une de l'autre sur la première couche active (21) ; l'électrode de grille (33) est disposée entre l'électrode de source (31) et l'électrode de drain (32) ; la seconde couche active (22) est disposée sur l'électrode de grille (33), l'électrode de source (31) et l'électrode de drain (32) ; à la fois l'électrode de source (31) et l'électrode de drain (32) sont connectées à la première couche active (21) et à la seconde couche active (22) ; et l'électrode de grille (33) est respectivement isolée de la première couche active (21), de la seconde électrode active (22), de l'électrode de source (31) et de l'électrode de drain (32) ; lorsqu'une tension est appliquée à l'électrode de grille (33), l'électrode de source (31) et l'électrode de drain (32) peuvent être reliées au moyen de la première couche active (21), et l'électrode de source (31) et l'électrode de drain (32) peuvent également être reliées au moyen de la deuxième couche active (22) ; à la fois l'électrode de source (31) et l'électrode de drain (32) peuvent être connectées simultanément au moyen de la première couche active (21) et de la seconde couche active (22) lorsque le transistor à couches minces est connecté, un courant plus important peut circuler entre l'électrode de source (31) et l'électrode de drain (32), de façon à augmenter le courant à l'état passant du transistor à couches minces.
(ZH) 一种薄膜晶体管及其制造方法、显示装置,属于半导体领域。该薄膜晶体管包括第一有源层(21)、源极(31)、漏极(32)、栅极(33)和第二有源层(22),其中,源极(31)、漏极(32)和栅极(33)间隔设置在第一有源层(21)上,栅极(33)位于源极(31)和漏极(32)之间,第二有源层(22)设置在栅极(33)、源极(31)和漏极(32)上,源极(31)和漏极(32)均与第一有源层(21)和第二有源层(22)连接,栅极(33)分别与第一有源层(21)、第二有源层(22)、源极(31)和漏极(32)绝缘,在栅极(33)上施加电压时,源极(31)和漏极(32)可以通过第一有源层(21)导通,源极(31)和漏极(32)还可以通过第二有源层(22)导通,由于源极(31)和漏极(32)在薄膜晶体管导通时,可以同时通过第一有源层(21)和第二有源层(22)导通,因此源极(31)和漏极(32)之间可以流通更大的电流,从而可以增大薄膜晶体管的开态电流。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)