Search International and National Patent Collections

1. (WO2018200578) ARCHITECTED STATE RETENTION

Pub. No.:    WO/2018/200578    International Application No.:    PCT/US2018/029211
Publication Date: Fri Nov 02 00:59:59 CET 2018 International Filing Date: Wed Apr 25 01:59:59 CEST 2018
IPC: G06F 1/32
Applicants: APPLE INC.
Inventors: SEMERIA, Bernard Joseph
MYLIUS, John H.
KANAPATHIPILLAI, Pradeep
RUSSO, Richard F.
WEN, Shih-Chieh
LARSON, Richard H.
Title: ARCHITECTED STATE RETENTION
Abstract:
Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.