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1. (WO2018200243) METHODS FOR DETECTING AN IMMINENT POWER FAILURE IN TIME TO PROTECT LOCAL DESIGN STATE
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Pub. No.: WO/2018/200243 International Application No.: PCT/US2018/027805
Publication Date: 01.11.2018 International Filing Date: 16.04.2018
IPC:
G06F 1/30 (2006.01) ,G06F 1/32 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
30
Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
32
Means for saving power
Applicants:
QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
BATENBURG, Michael Kevin; US
LE ROY, Vincent Pierre; US
ORIGANTI, Praveen Kumar; US
Agent:
WORLEY, Eugene; US
Priority Data:
15/499,45027.04.2017US
Title (EN) METHODS FOR DETECTING AN IMMINENT POWER FAILURE IN TIME TO PROTECT LOCAL DESIGN STATE
(FR) PROCÉDÉS DE DÉTECTION D'UNE PANNE DE COURANT IMMINENTE À LE TEMPS POUR PROTÉGER UN ÉTAT DE CONCEPTION LOCALE
Abstract:
(EN) In certain aspects of the disclosure, a chip includes an isolation device, wherein the isolation device is configured to allow a signal to pass from a first circuit in a first power domain to a second circuit in a second power domain via a signal line that crosses between the first and second power domains when the isolation device is disabled, and to clamp a portion of the signal line in the second power domain to a logic state when the isolation device is enabled. The chip also includes a failure detector configured to detect an imminent power failure of at least one of the first power domain or the second power domain, and to enable the isolation device in response to detection of the imminent power failure.
(FR) L'invention concerne une puce comprenant un dispositif d'isolation, le dispositif d'isolation étant configuré pour permettre à un signal de passer d'un premier circuit dans un premier domaine de puissance à un second circuit dans un second domaine de puissance par l'intermédiaire d'une ligne de signal qui traverse entre les premier et second domaines de puissance lorsque le dispositif d'isolation est désactivé, et pour fixer une partie de la ligne de signal dans le second domaine de puissance à un état logique lorsque le dispositif d'isolation est activé. La puce comprend également un détecteur de panne configuré pour détecter une panne de courant imminente d'au moins l'un du premier domaine de puissance ou du second domaine de puissance, et pour activer le dispositif d'isolation en réponse à la détection de la panne de courant imminente.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)