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1. (WO2018199646) MEMORY DEVICE ACCESSED ON BASIS OF DATA LOCALITY AND ELECTRONIC SYSTEM INCLUDING SAME
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Pub. No.: WO/2018/199646 International Application No.: PCT/KR2018/004850
Publication Date: 01.11.2018 International Filing Date: 26.04.2018
IPC:
G06F 12/02 (2006.01) ,G06F 13/16 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
16
for access to memory bus
Applicants:
공재섭 KONG, Jaesop [KR/KR]; KR
Inventors:
공재섭 KONG, Jaesop; KR
Agent:
박영우 PARK, Young-woo; KR
Priority Data:
10-2017-005468027.04.2017KR
15/851,77522.12.2017US
Title (EN) MEMORY DEVICE ACCESSED ON BASIS OF DATA LOCALITY AND ELECTRONIC SYSTEM INCLUDING SAME
(FR) DISPOSITIF DE MÉMOIRE ACCESSIBLE SUR LA BASE DE L'EMPLACEMENT DES DONNÉES ET SYSTÈME ÉLECTRONIQUE COMPRENANT LEDIT DISPOSITIF
(KO) 데이터 구역성을 고려하여 액세스되는 메모리 장치 및 이를 포함하는 전자 시스템
Abstract:
(EN) A memory device comprises a memory cell array, a row decoder, a multiplex column decoder, a gating circuit, and an input/output data driving circuit. The memory cell array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The row decoder generates a row selection signal for selecting a target row among a plurality of rows on the basis of a row address. The multiplex column decoder generates a multiplex column selection signal for simultaneously selecting a plurality of target columns among columns included in the target row on the basis of a column address and column selection information. The gating circuit simultaneously selects a plurality of target columns on the basis of the multiplex column selection signal. On the basis of the multiplex column selection signal and a data mask signal, the input/output data driving circuit simultaneously writes input data to a plurality of target columns through the gating circuit or simultaneously outputs, as output data, data stored in a plurality of target columns through the gating circuit. Column addresses corresponding to a plurality of target columns included in a target row are not continuous.
(FR) L'invention concerne un dispositif de mémoire comprenant un réseau de cellules de mémoire, un décodeur de rangées, un décodeur de colonnes multiplex, un circuit de déclenchement et un circuit de commande de données d'entrée/sortie. Le réseau de cellules de mémoire comprend une pluralité de cellules de mémoire agencées en une pluralité de rangées et une pluralité de colonnes. Le décodeur de rangées génère un signal de sélection de rangée pour sélectionner une rangée cible parmi une pluralité de rangées sur la base d'une adresse de rangée. Le décodeur de colonne multiplex génère un signal de sélection de colonne multiplex pour sélectionner simultanément une pluralité de colonnes cibles parmi des colonnes incluses dans la rangée cible, sur la base d'une adresse de colonne et d'informations de sélection de colonne. Le circuit de déclenchement sélectionne simultanément une pluralité de colonnes cibles sur la base du signal de sélection de colonne multiplex. Sur la base du signal de sélection de colonne multiplex et d'un signal de masque de données, le circuit de commande de données d'entrée/de sortie écrit simultanément les données d'entrée dans une pluralité de colonnes cibles par l'intermédiaire du circuit de déclenchement, ou émet simultanément en tant que données de sortie des données stockées dans une pluralité de colonnes cibles, par l'intermédiaire du circuit de déclenchement. Les adresses de colonne correspondant à une pluralité de colonnes cibles incluses dans une rangée cible ne sont pas continues.
(KO) 메모리 장치는 메모리 셀 어레이, 행 디코더, 다중 열 디코더, 게이팅 회로 및 입출력 데이터 구동 회로를 포함한다. 메모리 셀 어레이는 복수의 행들 및 복수의 열들을 형성하도록 배열되는 복수의 메모리 셀들을 포함한다. 행 디코더는 행 어드레스에 기초하여, 복수의 행들 중 목표 행을 선택하기 위한 행 선택 신호를 발생한다. 다중 열 디코더는 열 어드레스 및 열 선택 정보에 기초하여, 목표 행에 포함되는 열들 중 복수의 목표 열들을 한 번에 선택하기 위한 다중 열 선택 신호를 발생한다. 게이팅 회로는 다중 열 선택 신호에 기초하여 복수의 목표 열들을 한 번에 선택한다. 입출력 데이터 구동 회로는 다중 열 선택 신호 및 데이터 마스크 신호에 기초하여, 게이팅 회로를 통해 복수의 목표 열들에 입력 데이터를 한 번에 기입하거나 복수의 목표 열들에 저장된 데이터를 한 번에 출력 데이터로서 출력한다. 목표 행에 포함되는 복수의 목표 열들에 대응하는 열 어드레스는 연속적이지 않다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)