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1. (WO2018198802) SOLID-STATE IMAGE CAPTURE DEVICE AND IMAGE CAPTURE DEVICE
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Pub. No.: WO/2018/198802 International Application No.: PCT/JP2018/015409
Publication Date: 01.11.2018 International Filing Date: 12.04.2018
IPC:
H01L 27/146 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01) ,H04N 5/369 (2011.01) ,H04N 5/374 (2011.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
374
Addressed sensors, e.g. MOS or CMOS sensors
Applicants:
パナソニックIPマネジメント株式会社 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. [JP/JP]; 大阪府大阪市中央区城見2丁目1番61号 1-61, Shiromi 2-chome, Chuo-ku, Osaka-shi, Osaka 5406207, JP
Inventors:
清水 祐介 SHIMIZU Yuusuke; --
小野澤 和利 ONOZAWA Kazutoshi; --
Agent:
鎌田 健司 KAMATA Kenji; JP
前田 浩夫 MAEDA Hiroo; JP
Priority Data:
2017-08617625.04.2017JP
Title (EN) SOLID-STATE IMAGE CAPTURE DEVICE AND IMAGE CAPTURE DEVICE
(FR) DISPOSITIF DE CAPTURE D'IMAGE À SEMI-CONDUCTEURS ET DISPOSITIF DE CAPTURE D'IMAGE
(JA) 固体撮像装置および撮像装置
Abstract:
(EN) A solid-state image capture device (1) comprises: a first semiconductor substrate (10) including a pixel array section (12) in which a plurality of pixels are arranged in a matrix, and a first connection section (130); and a second semiconductor substrate (20) for controlling the pixel array section (12), the second semiconductor substrate (20) including a pad section (250) comprising a plurality of pad electrodes (259) for external electrical connection, and a second connection section (230). The first semiconductor substrate (10) and the second semiconductor substrate (20) are stacked one upon the other and bonded to each other. The first connection section (130) and the second connection section (230) are electrically connected to each other. The first semiconductor substrate (10) has substantially the same size as the second semiconductor substrate (20). The pad electrodes (259) are only provided in the second semiconductor substrate (20).
(FR) L'invention concerne un dispositif de capture d'image à semi-conducteurs (1) comprenant : un premier substrat semi-conducteur (10) comprenant une section de réseau de pixels (12) dans laquelle une pluralité de pixels sont agencés dans une matrice, et une première section de connexion (130) ; et un second substrat semi-conducteur (20) pour commander la section de réseau de pixels (12), le second substrat semi-conducteur (20) comprenant une section de pastille (250) comprenant une pluralité d'électrodes pastilles (259) pour une connexion électrique externe, et une seconde section de connexion (230). Le premier substrat semi-conducteur (10) et le second substrat semi-conducteur (20) sont empilés l'un sur l'autre et liés l'un à l'autre. La première section de connexion (130) et la seconde section de connexion (230) sont électriquement connectées l'une à l'autre. Le premier substrat semi-conducteur (10) a sensiblement la même taille que le second substrat semi-conducteur (20). Les électrodes pastilles (259) sont disposées uniquement dans le second substrat semi-conducteur (20).
(JA) 固体撮像装置(1)は、複数の画素が行列状に配置された画素アレイ部(12)、および、第1の接続部(130)を有する第1の半導体基板(10)と、外部と電気的に接続するための複数のパッド電極(259)からなるパッド部(250)、および、第2の接続部(230)を有し、前記画素アレイ部(12)を制御する第2の半導体基板(20)とを備え、前記第1の半導体基板(10)と前記第2の半導体基板(20)とは積層かつ接合され、前記第1の接続部(130)と前記第2の接続部(230)とは電気的に接続されており、前記第1の半導体基板(10)は、前記第2の半導体基板(20)と実質的に同じサイズであり、前記パッド電極(259)は、前記第2の半導体基板(20)のみに有する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)