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1. (WO2018198753) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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Pub. No.: WO/2018/198753 International Application No.: PCT/JP2018/015058
Publication Date: 01.11.2018 International Filing Date: 10.04.2018
IPC:
H01S 5/02 (2006.01) ,H01L 21/301 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
S
DEVICES USING STIMULATED EMISSION
5
Semiconductor lasers
02
Structural details or components not essential to laser action
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
吉川 兼司 YOSHIKAWA, Kenji; JP
根岸 将人 NEGISHI, Masato; JP
鈴木 正人 SUZUKI, Masato; JP
吉野 達郎 YOSHINO, Tatsuro; JP
Agent:
特許業務法人深見特許事務所 FUKAMI PATENT OFFICE, P.C.; 大阪府大阪市北区中之島三丁目2番4号 中之島フェスティバルタワー・ウエスト Nakanoshima Festival Tower West, 2-4, Nakanoshima 3-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
Priority Data:
2017-08539824.04.2017JP
Title (EN) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体デバイスの製造方法
Abstract:
(EN) This method for manufacturing a semiconductor device (12) comprises: forming a plurality of semiconductor devices (12) in a first region (15) of a primary surface (11a) of a wafer (11); forming a plurality of cleavage starting point parts (20a-20g) in a second region (16), different from the first region (15), of the primary surface (11a); and using a plurality of cleavage starting point parts (20a-20g) as starting points to cleave the wafer (11) sequentially, starting from the cleavage starting point part (20d) that is relatively difficult to cleave among the plurality of cleavage starting point parts (20a-20g). The forming of the plurality of cleavage starting point parts (20a-20g) includes forming a plurality of first grooves (20a-20g) by etching a portion of the second region (16). Therefore, the yield and manufacturing efficiency of the semiconductor device can be improved.
(FR) La présente invention concerne un procédé de fabrication d'un dispositif à semi-conducteurs (12) qui consiste : à former une pluralité de dispositifs à semi-conducteurs (12) dans une première région (15) d'une surface primaire (11a) d'une tranche (11) ; à former une pluralité de parties de point de départ de clivage (20a-20g) dans une seconde région (16), différente de la première région (15), de la surface primaire (11a) ; et à utiliser une pluralité de parties de point de départ de clivage (20a-20g) en tant que points de départ pour couper la tranche (11) séquentiellement, en commençant par la partie de point de départ de clivage (20d) qui est relativement difficile à cliver parmi la pluralité de parties de point de départ de clivage (20a-20g). La formation de la pluralité de parties de point de départ de clivage (20a-20g) consiste à former une pluralité de premières rainures (20a-20g) par gravure d'une partie de la seconde région (16). Par conséquent, le rendement et l'efficacité de fabrication du dispositif à semi-conducteurs peuvent être améliorés.
(JA) 半導体デバイス(12)の製造方法は、ウエハ(11)の主面(11a)の第1の領域(15)に、複数の半導体デバイス(12)を形成することと、第1の領域(15)とは異なる主面(11a)の第2の領域(16)に複数の劈開起点部(20a-20g)を形成することと、複数の劈開起点部(20a-20g)のうち相対的に劈開され難い劈開起点部(20d)から順に、複数の劈開起点部(20a-20g)を起点としてウエハ(11)を劈開することとを備える。複数の劈開起点部(20a-20g)を形成することは、第2の領域(16)の一部をエッチングすることによって複数の第1の溝(20a-20g)を形成することを含む。そのため、半導体デバイスの収率と製造効率とを向上させることができる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)