Search International and National Patent Collections

1. (WO2018196654) RIPPLE SUPPRESSION CIRCUIT

Pub. No.:    WO/2018/196654    International Application No.:    PCT/CN2018/083338
Publication Date: Fri Nov 02 00:59:59 CET 2018 International Filing Date: Wed Apr 18 01:59:59 CEST 2018
IPC: H02M 7/217
H02M 1/14
Applicants: TRIDONIC GMBH & CO KG
MAO, Egbert
Inventors: MAO, Egbert
CHEN, Steven
ZHONG, Scotty
Title: RIPPLE SUPPRESSION CIRCUIT
Abstract:
A ripple suppression circuit comprising a first transistor, a second transistor and a third transistor; the first transistor being connected in series to the second transistor to form a Darlington transistor; and the third transistor being connected in parallel to the Darlington transistor formed by the first transistor and the second transistor to control on/off of the Darlington transistor.