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1. (WO2018196380) PIXEL DRIVING CIRCUIT AND DISPLAY PANEL
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Pub. No.: WO/2018/196380 International Application No.: PCT/CN2017/113946
Publication Date: 01.11.2018 International Filing Date: 30.11.2017
IPC:
G09G 3/32 (2016.01) ,G09G 3/3208 (2016.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
22
using controlled light sources
30
using electroluminescent panels
32
semiconductive, e.g. diodes
[IPC code unknown for G09G 3/3208]
Applicants:
深圳市华星光电半导体显示技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区公明街道塘明大道9-2号 No. 9-2, Tangming Rd, Gongming Street Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
陈小龙 CHEN, Xiaolong; CN
温亦谦 WEN, Yi-Chien; CN
周明忠 JOU, Ming-Jong; CN
Agent:
广州三环专利商标代理有限公司 SCIHEAD IP LAW FIRM; 中国广东省广州市 越秀区先烈中路80号汇华商贸大厦1508室 Room 1508, Huihua Commercial & Trade Building No. 80, XianLie Zhong Road, Yuexiu District Guangzhou, Guangdong 510070, CN
Priority Data:
201710297652.X28.04.2017CN
Title (EN) PIXEL DRIVING CIRCUIT AND DISPLAY PANEL
(FR) CIRCUIT D'ATTAQUE DE PIXEL ET PANNEAU D'AFFICHAGE
(ZH) 像素驱动电路和显示面板
Abstract:
(EN) A pixel driving circuit and a display panel (100), the pixel driving circuit comprising a driving transistor (T0), wherein the driving transistor (T0) is provided with a gate terminal (g), a source terminal (s) and a drain terminal (d). A first switch (T1) is arranged between the gate terminal (g) and the drain terminal (d), and the gate terminal (g) is connected to a reset voltage signal terminal (VREF) by means of a second switch (T2). The source terminal (s) is connected to a driving voltage signal terminal (OVDD) and a data voltage signal terminal (VDATA) by means of a third switch (T3) and a fourth switch (T4) respectively. A first capacitor (C11) is connected between the gate terminal (g) and a charging voltage terminal (n) that is connected to the control terminal of the first switch (T1), and a second capacitor (C12) is connected between the gate terminal (g) and the driving voltage signal terminal (OVDD).
(FR) L'invention concerne un circuit d'attaque de pixel et un panneau (100) d'affichage, le circuit d'attaque de pixel comportant un transistor (T0) d'attaque, le transistor (T0) d'attaque étant muni d'une borne de grille (g), d'une borne de source (s) et d'une borne de drain (d). Un premier commutateur (T1) est disposé entre la borne de grille (g) et la borne de drain (d), et la borne de grille (g) est reliée à une borne de signal de tension de réinitialisation (VREF) au moyen d'un second commutateur (T2). La borne de source (s) est reliée à une borne de signal de tension d'attaque (OVDD) et à une borne de signal de tension de données (VDATA) respectivement au moyen d'un troisième commutateur (T3) et d'un quatrième commutateur (T4). Un premier condensateur (C11) est branché entre la borne de grille (g) et une borne de tension de charge (n) qui est reliée à la borne de commande du premier commutateur (T1), et un second condensateur (C12) est branché entre la borne de grille (g) et la borne de signal de tension d'attaque (OVDD).
(ZH) 一种像素驱动电路和一种显示面板(100),像素驱动电路包括驱动晶体管(T0),驱动晶体管(T0)设有栅极端(g)、源极端(s)和漏极端(d)。栅极端(g)与漏极端(d)之间设置第一开关(T1),且栅极端(g)通过第二开关(T2)连接于复位电压信号端(VREF)。源极端(s)通过第三开关(T3)和第四开关(T4)分别连接于驱动电压信号端(OVDD)和数据电压信号端(VDATA)。第一电容(C11)连接于栅极端(g)和充电电压端(n)之间,充电电压端(n)连接于第一开关(T1)的控制端,第二电容(C12)连接于栅极端(g)和驱动电压信号端(OVDD)之间。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)