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1. (WO2018196087) ARRAY SUBSTRATE, DISPLAY APPARATUS AND MANUFACTURING METHOD THEREFOR
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Pub. No.: WO/2018/196087 International Application No.: PCT/CN2017/086232
Publication Date: 01.11.2018 International Filing Date: 27.05.2017
IPC:
H01L 21/77 (2017.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号 No.9-2 Tangming Rd Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
刘兆松 LIU, Zhaosong; CN
徐源竣 HSU, Yuan-Jun; CN
李松杉 LI, Songshan; CN
Agent:
深圳市威世博知识产权代理事务所(普通合伙) CHINA WISPRO INTELLECTUAL PROPERTY LLP.; 中国广东省深圳市 南山区高新区粤兴三道8号中国地质大学产学研基地中地大楼A806 Room A806, Zhongdi Building China University of Geosciences Base No.8 Yuexing 3rd Road, High-Tech Industrial Estate Nanshan District, Shenzhen, Guangdong 518057, CN
Priority Data:
201710294119.828.04.2017CN
Title (EN) ARRAY SUBSTRATE, DISPLAY APPARATUS AND MANUFACTURING METHOD THEREFOR
(FR) SUBSTRAT DE RÉSEAU, APPAREIL D'AFFICHAGE ET SON PROCÉDÉ DE FABRICATION
(ZH) 一种阵列基板、显示装置及其制作方法
Abstract:
(EN) An array substrate, a display apparatus and a manufacturing method therefor. The array substrate comprises a base substrate (10), and a low-temperature polysilicon transistor (20) and an oxide transistor (30) located above the base substrate (10). The low-temperature polysilicon transistor (20) comprises a polysilicon layer (21) and a first insulating layer (22) arranged in a stacked manner, wherein the first insulating layer (22) comprises a silicon oxide layer (222) and a silicon nitride layer (221), with the silicon nitride layer (221) being located between the polysilicon layer (21) and the silicon oxide layer (222). The oxide transistor (30) comprises an oxide semiconductor layer (31) and a second insulating layer (32) arranged in a stacked manner, wherein the second insulating layer (32) does not contain a silicon nitride layer. The present invention effectively solves the problem of electric leakage of a low-temperature polysilicon transistor, and improves the reliability of an oxide transistor.
(FR) La présente invention concerne un substrat de réseau, un appareil d’affichage et son procédé de fabrication. Le substrat de réseau comprend un substrat de base (10), et un transistor en polysilicium basse température (20) et un transistor à oxyde (30) situé au-dessus du substrat de base (10). Le transistor en polysilicium basse température (20) comprend une couche de polysilicium (21) et une première couche d'isolation (22) agencées de manière empilée, la première couche d'isolation (22) comprenant une couche d'oxyde de silicium (222) et une couche de nitrure de silicium (221), la couche de nitrure de silicium (221) étant située entre la couche de polysilicium (21) et la couche d'oxyde de silicium (222). Le transistor à oxyde (30) comprend une couche semi-conductrice d'oxyde (31) et une seconde couche d'isolation (32) agencées de manière empilée, la seconde couche d'isolation (32) ne contenant pas de couche de nitrure de silicium. La présente invention résout efficacement le problème de fuite électrique d'un transistor en polysilicium basse température, et améliore la fiabilité d'un transistor à oxyde.
(ZH) 一种阵列基板、显示装置及其制作方法。其中,阵列基板包括衬底基板(10)和位于衬底基板(10)上方的低温多晶硅晶体管(20)和氧化物晶体管(30);低温多晶硅晶体管(20)包括层叠设置的多晶硅层(21)和第一绝缘层(22),第一绝缘层(22)包括氧化硅层(222)以及氮化硅层(221),其中氮化硅层(221)位于多晶硅层(21)和氧化硅层(222)之间;氧化物晶体管(30)包括层叠设置的氧化物半导体层(31)和第二绝缘层(32),第二绝缘层(32)不含氮化硅层。有效降低了低温多晶硅晶体管的漏电问题,同时提高氧化物晶体管的可靠性。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)