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1. (WO2018196075) ARRAY SUBSTRATE, MANUFACTURING METHOD, AND DISPLAY DEVICE
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Pub. No.: WO/2018/196075 International Application No.: PCT/CN2017/085852
Publication Date: 01.11.2018 International Filing Date: 25.05.2017
IPC:
H01L 27/12 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号 No. 9-2, Tangming Rd, Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
李松杉 LI, Songshan; CN
徐源竣 HSU, Yuan-jun; CN
刘兆松 LIU, Zhaosong; CN
Agent:
深圳市威世博知识产权代理事务所 (普通合伙) CHINA WISPRO INTELLECTUAL PROPERTY LLP.; 中国广东省深圳市 南山区高新区粤兴三道8号中国地质大学产学研基地中地大楼A806 Room A806 Zhongdi Building China University of Geosciences Base, No. 8 Yuexing 3rd Road, High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201710295367.428.04.2017CN
Title (EN) ARRAY SUBSTRATE, MANUFACTURING METHOD, AND DISPLAY DEVICE
(FR) SUBSTRAT MATRICIEL, PROCÉDÉ DE FABRICATION ET DISPOSITIF D'AFFICHAGE
(ZH) 一种阵列基板及制备方法、显示装置
Abstract:
(EN) An array substrate, a manufacturing method, and a display device. The array substrate comprises: a channel layer (102); a gate insulating layer (103) comprising a first part (1031) and a second part (1032) that are connected side by side and disposed on the channel layer (102), and expose source and drain contact areas (1022) on the channel layer (102), the second part (1032) of the gate insulating layer (103) being located at two sides of the first part (1031) of the gate insulating layer (103); a gate layer (104) provided at the first part (1031) of the gate insulating layer (103); and a source (1051) and a drain (1052) that are respectively and correspondingly connected to the source and drain contact areas (1022) of the channel layer (102). The array substrate resolves the problem of electric leakage of the array substrate caused by the array substrate becoming a conductor because ion implantation is performed on the channel layer (102).
(FR) L'invention concerne un substrat matriciel, un procédé de fabrication et un dispositif d’affichage. Le substrat matriciel comprend : une couche de canal (102) ; une couche d'isolation de grille (103) comprenant une première partie (1031) et une seconde partie (1032) qui sont reliées côte à côte et disposées sur la couche de canal (102), et le procédé consiste à exposer des zones de contact de source et de drain (1022) sur la couche de canal (102), la seconde partie (1032) de la couche d'isolation de grille (103) étant située au niveau de deux côtés de la première partie (1031) de la couche d'isolation de grille (103) ; une couche de grille (104) disposée au niveau de la première partie (1031) de la couche d'isolation de grille (103) ; et une source (1051) et un drain (1052) qui sont respectivement connectés de manière correspondante aux zones de contact de source et de drain (1022) de la couche de canal (102). Le substrat matriciel résout le problème de fuite électrique du substrat matriciel provoqué par le fait que le substrat matriciel se transforme en un conducteur étant donné qu'une implantation ionique est appliquée à la couche de canal (102).
(ZH) 一种阵列基板及制备方法、显示装置,阵列基板包括:沟道层(102);栅极绝缘层(103),包括并排连接的第一部分(1031)和第二部分(1032),设置于沟道层(102)上,并且暴露出沟道层(102)上的源极和漏极接触区(1022),栅极绝缘层(103)的第二部分(1032)位于栅极绝缘层(103)的第一部分(1031)两侧;栅极层(104),设置于栅极绝缘层(103)的第一部分(1031);源极(1051)和漏极(1052),与沟道层(102)的源极和漏极接触区(1022)分别对应连接。阵列基板解决因沟道层(102)进行离子注入使其导体化导致阵列基板漏电的问题。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)