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1. (WO2018189964) MAGNETIC DOMAIN WALL UTILIZING ANALOG MEMORY ELEMENT, MAGNETIC DOMAIN WALL UTILIZING ANALOG MEMORY, NON-VOLATILE LOGIC CIRCUIT AND MAGNETIC NEURO-ELEMENT
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/189964 International Application No.: PCT/JP2017/046623
Publication Date: 18.10.2018 International Filing Date: 26.12.2017
IPC:
H01L 21/8239 (2006.01) ,H01L 27/105 (2006.01) ,H01L 29/82 (2006.01) ,H01L 43/08 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
82
controllable by variation of the magnetic field applied to the device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08
Magnetic-field-controlled resistors
Applicants:
TDK株式会社 TDK CORPORATION [JP/JP]; 東京都中央区日本橋二丁目5番1号 2-5-1, Nihonbashi, Chuo-ku, Tokyo 1036128, JP
Inventors:
佐々木 智生 SASAKI Tomoyuki; JP
柴田 竜雄 SHIBATA Tatsuo; JP
Agent:
棚井 澄雄 TANAI Sumio; JP
荒 則彦 ARA Norihiko; JP
飯田 雅人 IIDA Masato; JP
荻野 彰広 OGINO Akihiro; JP
Priority Data:
2017-08041314.04.2017JP
Title (EN) MAGNETIC DOMAIN WALL UTILIZING ANALOG MEMORY ELEMENT, MAGNETIC DOMAIN WALL UTILIZING ANALOG MEMORY, NON-VOLATILE LOGIC CIRCUIT AND MAGNETIC NEURO-ELEMENT
(FR) PAROI DE DOMAINE MAGNÉTIQUE UTILISANT UN ÉLÉMENT DE MÉMOIRE ANALOGIQUE, PAROI DE DOMAINE MAGNÉTIQUE UTILISANT UNE MÉMOIRE ANALOGIQUE, CIRCUIT LOGIQUE NON VOLATILE ET NEURO-ÉLÉMENT MAGNÉTIQUE
(JA) 磁壁利用型アナログメモリ素子、磁壁利用型アナログメモリ、不揮発性ロジック回路及び磁気ニューロ素子
Abstract:
(EN) The magnetic domain wall utilizing analog memory element according to one mode of the present invention comprises: a magnetized fixed layer (1) wherein the magnetization is oriented in a first direction; a non-magnetic layer (2) provided on one surface of the magnetized fixed layer (1); a magnetic domain wall drive layer (3) provided relative to the magnetized fixed layer (1) such that the non-magnetic layer (2) is held therebetween; a first magnetization supply means (4) supplying to the magnetic domain wall drive layer (3) magnetization oriented in the first direction; and a second magnetization supply means (5) supplying to the magnetic domain wall drive layer (3) magnetization oriented in a second direction opposite the first direction. At least one among the first magnetization supply means (4) and the second magnetization supply means (5) is in contact with the magnetic domain wall drive layer (3), and is a spin orbit torque wiring extending in a direction intersecting with the magnetic domain wall drive layer (3).
(FR) La paroi de domaine magnétique utilisant un élément de mémoire analogique selon un mode de la présente invention comprend : une couche fixe magnétisée (1) dans laquelle la magnétisation est orientée dans une première direction; une couche non magnétique (2) disposée sur une surface de la couche fixe magnétisée (1); une couche d'entraînement de paroi de domaine magnétique (3) disposée par rapport à la couche fixe magnétisée (1) de telle sorte que la couche non magnétique (2) est maintenue entre celles-ci; un premier moyen d'alimentation en magnétisation (4) fournissant à la couche d'entraînement de paroi de domaine magnétique (3) une magnétisation orientée dans la première direction; et un second moyen d'alimentation en magnétisation (5) fournissant à la couche d'entraînement de paroi de domaine magnétique (3) une magnétisation orientée dans une seconde direction opposée à la première direction. Au moins l'un parmi le premier moyen d'alimentation en magnétisation (4) et le second moyen d'alimentation en magnétisation (5) est en contact avec la couche d'entraînement de paroi de domaine magnétique (3), et est un câblage de couple spin-orbite s'étendant dans une direction croisant la couche d'entraînement de paroi de domaine magnétique (3).
(JA) 本発明の一態様にかかる磁壁利用型アナログメモリ素子は、第1の方向に磁化が配向した磁化固定層(1)と、磁化固定層(1)の一面に設けられた非磁性層(2)と、磁化固定層(1)に対して非磁性層(2)を挟んで設けられた磁壁駆動層(3)と、磁壁駆動層(3)に第1の方向に配向した磁化を供給する第1磁化供給手段(4)及び第1の方向と反対の第2の方向に配向した磁化を供給する第2磁化供給手段(5)と、を備え、第1磁化供給手段(4)及び第2磁化供給手段(5)のうち少なくとも一方は、磁壁駆動層(3)に接し、磁壁駆動層(3)に対して交差する方向に延在するスピン軌道トルク配線である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN109643690US20190189516