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1. (WO2018186196) SOLID STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/186196 International Application No.: PCT/JP2018/011569
Publication Date: 11.10.2018 International Filing Date: 23.03.2018
IPC:
H01L 27/146 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 21/822 (2006.01) ,H01L 23/522 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01) ,H01L 27/00 (2006.01) ,H01L 27/04 (2006.01) ,H04N 5/369 (2011.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
橋口 日出登 HASHIGUCHI, Hideto; JP
庄子 礼二郎 SHOHJI, Reijiroh; JP
堀越 浩 HORIKOSHI, Hiroshi; JP
三橋 生枝 MITSUHASHI, Ikue; JP
飯島 匡 IIJIMA, Tadashi; JP
亀嶋 隆季 KAMESHIMA, Takatoshi; JP
石田 実 ISHIDA, Minoru; JP
羽根田 雅希 HANEDA, Masaki; JP
Agent:
特許業務法人酒井国際特許事務所 SAKAI INTERNATIONAL PATENT OFFICE; JP
Priority Data:
2017-07480604.04.2017JP
2017-15658614.08.2017JP
Title (EN) SOLID STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
(FR) DISPOSITIF D'IMAGERIE À SEMI-CONDUCTEURS ET APPAREIL ÉLECTRONIQUE
(JA) 固体撮像装置、及び電子機器
Abstract:
(EN) [Problem] To provide a solid state imaging device and an electronic apparatus that have improved performance. [Solution] A solid state imaging device that is formed by laminating, in order, a first substrate, a second substrate, and a third substrate. The first substrate is formed by laminating a first semiconductor substrate and a first multilayer wiring layer and has formed thereon a pixel unit that comprises an array of pixels. The second substrate is formed by laminating a second semiconductor substrate and a second multilayer wiring layer and has formed thereon a circuit that has a prescribed function. The third substrate is formed by laminating a third semiconductor substrate and a third multilayer wiring layer and has formed thereon a circuit that has a prescribed function. The first substrate and the second substrate are adhered to each other such that the first multilayer wiring layer and the second semiconductor substrate face. A first connection structure that is for electrically connecting a circuit on the first substrate and the circuit on the second substrate does not include a connection structure that is mediated by an adhesion surface between the first substrate and the second substrate that is formed with the first substrate as a point of reference, or there is no first connection structure.
(FR) L'invention vise à améliorer les performances d'un dispositif d'imagerie à semi-conducteurs et d'un appareil électronique. Plus spécifiquement, l'invention concerne un dispositif d'imagerie à semi-conducteurs constitué, stratifiés dans l'ordre suivant: d'un premier substrat dans lequel est formée une partie pixels dans laquelle des pixels sont alignés, et lequel substrat est constitué à son tour d'un premier substrat à semi-conducteurs et d'une première couche de câblage multicouche stratifiés; d'un deuxième substrat dans lequel est formé un circuit avec une fonction prédéterminée, et lequel substrat est constitué à son tour d'un deuxième substrat à semi-conducteurs et d'une deuxième couche de câblage multicouche stratifiés; et d'un troisième substrat dans lequel est formé un circuit avec une fonction prédéterminée, et lequel substrat est constitué à son tour d'un troisième substrat à semi-conducteurs et d'une troisième couche de câblage multicouche stratifiés. Les premier substrat et deuxième substrat susmentionnés sont collés de façon que la première couche de câblage multicouche et la deuxième couche de câblage multicouche soient opposées l'une à l'autre. Le dispositif d'imagerie à semi-conducteurs possède première une structure de connexion pour la connexion électrique du circuit du premier substrat et du circuit du deuxième substrat. Cette première structure de connexion ne contient pas de structure de connexion formée en tant que base du premier substrat et mettant en oeuvre une surface d'adhésion entre le premier substrat et le deuxième substrat susmentionnés, ou alternativement, le dispositif d'imagerie à semi-conducteurs ne contient pas de première structure de connexion.
(JA) 【課題】性能がより向上した固体撮像装置及び電子機器を提供する。 【解決手段】画素が配列された画素部が形成され、第1半導体基板及び第1多層配線層が積層された第1基板と、所定の機能を有する回路が形成され、第2半導体基板及び第2多層配線層が積層された第2基板と、所定の機能を有する回路が形成され、第3半導体基板及び第3多層配線層が積層された第3基板と、がこの順に積層されて構成され、前記第1基板と前記第2基板とは、前記第1多層配線層と前記第2半導体基板とが対向するように貼り合わされ、前記第1基板の回路と前記第2基板の回路とを電気的に接続するための第1の接続構造は、前記第1基板を基点として形成される前記第1基板と前記第2基板との貼り合わせ面を介した接続構造を含まない、又は、前記第1の接続構造が、存在しない、固体撮像装置。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)