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1. (WO2018186026) SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
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Pub. No.: WO/2018/186026 International Application No.: PCT/JP2018/005279
Publication Date: 11.10.2018 International Filing Date: 15.02.2018
IPC:
H01L 21/3205 (2006.01) ,H01L 21/02 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01) ,H01L 27/146 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
長濱 嘉彦 NAGAHAMA, Yoshihiko; JP
Agent:
亀谷 美明 KAMEYA, Yoshiaki; JP
金本 哲男 KANEMOTO, Tetsuo; JP
萩原 康司 HAGIWARA, Yasushi; JP
松本 一騎 MATSUMOTO, Kazunori; JP
Priority Data:
2017-07480104.04.2017JP
2017-08068914.04.2017JP
Title (EN) SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR, PROCÉDÉ DE FABRICATION ASSOCIÉ ET DISPOSITIF ÉLECTRONIQUE
(JA) 半導体装置、半導体装置の製造方法、及び電子機器
Abstract:
(EN) [PROBLEM] To further improve reliability of a semiconductor device. [SOLUTION] Provided is a semiconductor device configured by laminating a plurality of substrates each having a semiconductor substrate in which a circuit having a predetermined function is formed, and a multilayer wiring layer laminated on the semiconductor substrate, wherein: on an adhesion surface between at least two of the plurality of substrates, an electrode bonding structure in which electrodes formed on the bonding surface are bonded while being in direct contact with each other is present as a structure for electrically connecting the two substrates; and in at least one of the two substrates, for at least any one among an electrode constituting the electrode bonding structure and a via for connecting the electrode to wiring in the multilayer wiring layer, a structure, in which a protective film for preventing diffusion of a conductive material is buried, is present inside the conductive material constituting the electrode and the via.
(FR) La présente invention a pour objet d'améliorer la fiabilité d'un dispositif semi-conducteur. L'invention concerne un dispositif semi-conducteur configuré par stratification d'une pluralité de substrats comprenant chacun un substrat semi-conducteur dans lequel un circuit doté d'une fonction prédéterminée est formé, et d'une couche de câblage multicouche stratifiée sur le substrat semi-conducteur. Selon l'invention, sur une surface d'adhérence entre au moins deux substrats de la pluralité, une structure de liaison d'électrodes dans laquelle des électrodes formées sur la surface de liaison sont liées tout en étant en contact direct l'une avec l'autre est présente sous la forme d'une structure destinée à raccorder électriquement les deux substrats ; et dans au moins un des deux substrats, pour au moins une électrode constituant la structure de liaison d'électrodes ou un trou d'interconnexion permettant le raccordement de l'électrode au câblage dans la couche de câblage multicouche, une structure, dans laquelle est enfoui un film de protection destiné à empêcher la diffusion d'un matériau conducteur, est présente à l'intérieur du matériau conducteur constituant l'électrode et le trou d'interconnexion.
(JA) 【課題】半導体装置において、信頼性をより向上させることを可能にする。 【解決手段】所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層される多層配線層と、をそれぞれ有する複数の基板が積層されて構成され、前記複数の基板のうちの少なくとも2つの基板間の貼り合わせ面には、当該2つの基板間を電気的に接続するための構造であって、前記貼り合わせ面にそれぞれ形成される電極同士が直接接触した状態で接合している電極接合構造が存在し、前記2つの基板のうちの少なくともいずれかにおいて、前記電極接合構造を構成する電極、及び前記電極を前記多層配線層内の配線に接続するためのビアの少なくともいずれかについて、前記電極及び前記ビアを構成する導電材料の内部に当該導電材料の拡散を防止するための保護膜が埋め込まれた構造が存在する、半導体装置を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)