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1. (WO2018184403) THIN-FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE
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Pub. No.: WO/2018/184403 International Application No.: PCT/CN2017/116903
Publication Date: 11.10.2018 International Filing Date: 18.12.2017
IPC:
H01L 27/12 (2006.01) ,H01L 29/786 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
XU, Pan; CN
LI, Yongqian; CN
YUAN, Zhidong; CN
CAI, Zhenfei; CN
YUAN, Can; CN
LI, Meng; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan Chen, 10th Floor, Tower D Minsheng Financial Center 28 Jianguomennei Avenue Dongcheng District, Beijing 100005, CN
Priority Data:
201710221302.506.04.2017CN
Title (EN) THIN-FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE
(FR) TRANSISTOR À COUCHES MINCES ET SON PROCÉDÉ DE FABRICATION, SUBSTRAT DE RÉSEAU ET DISPOSITIF D'AFFICHAGE
Abstract:
(EN) A thin-film transistor includes a substrate (01), a light-shielding layer (02) and an active layer (04) sequentially over the substrate (01). The light-shielding layer (02) has an accommodating space having a bottom wall and a side wall on an upper surface thereof. An orthographic projection of the active layer (04) on the substrate (01) is contained within an orthographic projection of the accommodating space of the light-shielding layer (02). An upper side of the side wall of the accommodating space of the light-shielding layer (02) has a larger distance to the substrate than a bottom surface, and optionally has an equal or larger distance to the substrate (01) than a top surface of the active layer (04). The light-shielding layer (02) can comprise a gate electrode. As such, lights from an underneath and from a lateral side of the thin-film transistor that otherwise reach the active layer can be partially or completely blocked.
(FR) L'invention concerne un transistor à couches minces comprend un substrat (01), une couche de protection contre la lumière (02) et une couche active (04), disposées séquentiellement sur le substrat (01). La couche de protection contre la lumière (02) comporte un espace de réception ayant une paroi inférieure et une paroi latérale sur une surface supérieure de celle-ci. Une projection orthographique de la couche active (04) sur le substrat (01) est contenue dans une projection orthographique de l'espace de réception de la couche de protection contre la lumière (02). Un côté supérieur de la paroi latérale de l'espace de réception de la couche de protection contre la lumière (02) présente une distance au substrat plus grande qu'une surface inférieure et, facultativement, une distance au substrat (01) égale ou supérieure à celle d'une surface supérieure de la couche active (04). La couche de protection contre la lumière (02) peut comprendre une électrode de gâchette. Des rayons lumineux en provenance d'un côté inférieur et d'un côté latéral du transistor à couches minces qui, autrement, atteignent la couche active peuvent ainsi être partiellement ou complètement bloqués.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)