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1. (WO2018183787) ELECTRICAL CIRCUIT BOARD WITH LOW THERMAL CONDUCTIVITY AND METHOD OF CONSTRUCTING THEREOF
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Pub. No.: WO/2018/183787 International Application No.: PCT/US2018/025317
Publication Date: 04.10.2018 International Filing Date: 30.03.2018
IPC:
H05K 1/02 (2006.01) ,H05K 3/02 (2006.01) ,H05K 3/38 (2006.01) ,H05K 1/03 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
02
in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
38
Improvement of the adhesion between the insulating substrate and the metal
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
03
Use of materials for the substrate
Applicants:
KOZLOWSKI, Eric [US/US]; US (US)
DAVIS, Jason [US/US]; US (US)
PETERS, Larry Jr. [US/US]; US (US)
MAGNA SEATING INC. [CA/CA]; 337 Magna Drive Aurora, Ontario L4G 7K1, CA
Inventors:
KOZLOWSKI, Eric; US
DAVIS, Jason; US
PETERS, Larry Jr.; US
Agent:
ASHER, Robin, W.; US
Priority Data:
62/479,45231.03.2017US
Title (EN) ELECTRICAL CIRCUIT BOARD WITH LOW THERMAL CONDUCTIVITY AND METHOD OF CONSTRUCTING THEREOF
(FR) CARTE DE CIRCUIT ÉLECTRIQUE À FAIBLE CONDUCTIVITÉ THERMIQUE ET SON PROCÉDÉ DE CONSTRUCTION
Abstract:
(EN) An electrical circuit board includes a first conductive layer and a second conductive layer. And an interlayer forming a thermal barrier is placed between the first conductive layer and the second conductive layer, wherein the thermal barrier reduces heat transfer between the first conductive layer and the second conductive layer.
(FR) L'invention concerne une carte de circuit électrique qui comprend une première couche conductrice et une seconde couche conductrice. Et une couche intermédiaire formant une barrière thermique est placée entre la première couche conductrice et la seconde couche conductrice, la barrière thermique réduisant le transfert de chaleur entre la première couche conductrice et la seconde couche conductrice.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)