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1. (WO2018182962) BOOST CHARGE RECYCLE FOR LOW-POWER MEMORY
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/182962 International Application No.: PCT/US2018/022065
Publication Date: 04.10.2018 International Filing Date: 12.03.2018
Chapter 2 Demand Filed: 09.08.2018
IPC:
G11C 7/12 (2006.01) ,G11C 7/22 (2006.01) ,G11C 11/419 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
12
Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
22
Read-write (R-W) timing or clocking circuits; Read-write (R-W) control signal generators or management
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
41
forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417
for memory cells of the field-effect type
419
Read-write (R-W) circuits
Applicants: QUALCOMM INCORPORATED[US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors: SINHA, Rakesh Kumar; US
MATHURIA, Priyankar; US
GUPTA, Sharad Kumar; US
HOLLA VAKWADI, Lakshmikantha; US
Agent: HALLMAN, Jonathan W.; US
Priority Data:
15/476,74631.03.2017US
Title (EN) BOOST CHARGE RECYCLE FOR LOW-POWER MEMORY
(FR) RECYCLAGE DE CHARGE DE SURALIMENTATION POUR MÉMOIRE À FAIBLE PUISSANCE
Abstract:
(EN) A negative bit line boost circuit for a memory is configured to control a write multiplexer and a write assist transistor so that charge from a boost capacitor positively charges a bit line following a write assist period.
(FR) L'invention concerne un circuit d'amplification de ligne de bit négatif destiné à une mémoire qui est configuré afin de commander un multiplexeur d'écriture et un transistor d'aide à l'écriture de sorte que la charge provenant d'un condensateur d'amplification charge positivement une ligne de bit suite à une période d'aide à l'écriture.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)