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1. (WO2018182961) HIGH-SPEED LEVEL SHIFTER
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/182961 International Application No.: PCT/US2018/022018
Publication Date: 04.10.2018 International Filing Date: 12.03.2018
IPC:
H03K 3/356 (2006.01) ,G11C 5/14 (2006.01) ,G11C 7/12 (2006.01) ,G11C 8/10 (2006.01) ,H03K 19/0185 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
353
by the use, as active elements, of field-effect transistors with internal or external positive feedback
356
Bistable circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
14
Power supply arrangements
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
12
Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
8
Arrangements for selecting an address in a digital store
10
Decoders
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175
Coupling arrangements; Interface arrangements
0185
using field-effect transistors only
Applicants: QUALCOMM INCORPORATED[US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors: JUNG, Chulmin; US
CHEN, Po-Hung; US
AHMED, Fahad; US
JUNG, Changho; US
YOON, Sei Seung; US
LI, David; US
Agent: TSENG, George; US
Priority Data:
15/473,12429.03.2017US
Title (EN) HIGH-SPEED LEVEL SHIFTER
(FR) DISPOSITIF DE DÉCALAGE DE NIVEAU À GRANDE VITESSE
Abstract:
(EN) A circuit (200) including an output node (OUT) and a cross-coupled pair of semiconductor devices (204, 214) configured to provide, at the output node, an output signal in a second voltage domain (VDDH) based on an input signal in a first voltage domain (VDDL) is described herein. The circuit further includes a pull-up assist circuit (230) coupled to the output node; and a look-ahead circuit (220) coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.
(FR) La présente invention concerne un circuit (200) qui comprend un nœud de sortie (SORTIE) et une paire à couplage transversal de dispositifs à semi-conducteurs (204, 214) configurés de façon à fournir, au niveau du nœud de sortie, un signal de sortie dans un second domaine de tension (VDDH) sur la base d'un signal d'entrée dans un premier domaine de tension (VDDL). Le circuit comprend en outre un circuit d'assistance d'élévation (230) couplé au nœud de sortie, et un circuit d'anticipation (220) couplé au circuit d'assistance d'élévation, le circuit d'anticipation étant configuré de façon à amener le circuit d'assistance d'élévation à augmenter un niveau de tension au niveau du nœud de sortie lors d'une diminution d'un niveau de tension d'un signal de sortie inversé dans le second domaine de tension d'un niveau de tension élevé du second domaine de tension à un niveau de tension faible du second domaine de tension.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)