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1. (WO2018182922) SYSTEM AND METHOD FOR GENERATING RANDOM NUMBERS BASED ON NON-VOLATILE MEMORY CELL ARRAY ENTROPY
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Pub. No.: WO/2018/182922 International Application No.: PCT/US2018/020628
Publication Date: 04.10.2018 International Filing Date: 02.03.2018
IPC:
G01R 19/00 (2006.01) ,G06F 1/02 (2006.01) ,G06F 17/10 (2006.01) ,G06F 17/11 (2006.01) ,G06N 5/02 (2006.01) ,H01L 27/115 (2017.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
19
Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
02
Digital function generators
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
10
Complex mathematical operations
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
10
Complex mathematical operations
11
for solving equations
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
5
Computer systems utilizing knowledge based models
02
Knowledge representation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
Applicants: SILICON STORAGE TECHNOLOGY, INC.[US/US]; 450 Holger Way San Jose, CA 95134, US
Inventors: TIWARI, Vipin; US
REITEN, Mark; US
Agent: LIMBACH, Alan, A.; US
Priority Data:
15/905,72026.02.2018US
62/479,19330.03.2017US
Title (EN) SYSTEM AND METHOD FOR GENERATING RANDOM NUMBERS BASED ON NON-VOLATILE MEMORY CELL ARRAY ENTROPY
(FR) SYSTÈME ET PROCÉDÉ DE GÉNÉRATION DE NOMBRES ALÉATOIRES EN FONCTION D'UNE ENTROPIE DE RÉSEAU DE CELLULES DE MÉMOIRE NON VOLATILE
Abstract:
(EN) A memory device that generates a unique identifying number, and includes a plurality of memory cells and a controller. Each of the memory cells includes first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region. The controller is configured to apply one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions, measure the leakage currents, and generate a number based on the measured leakage currents.
(FR) L'invention concerne un dispositif de mémoire générant un numéro d'identification unique et comprenant une pluralité de cellules de mémoire et un dispositif de commande. Chacune des cellules de mémoire comprend des première et seconde zones formées dans un substrat semi-conducteur, une zone de canal du substrat s'étendant entre les première et seconde zones, une grille flottante étant disposée sur une première partie de la zone de canal et isolée de cette dernière, et une grille de sélection étant disposée sur une seconde partie de la zone de canal et isolée de cette dernière. Le dispositif de commande est conçu pour appliquer une ou plusieurs tensions positives aux premières zones des cellules de mémoire pendant que les cellules de mémoire sont dans un état de sous-seuil afin de générer un courant de fuite à travers chacune des zones de canal, mesurer les courants de fuite et générer un nombre en fonction des courants de fuite mesurés.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)