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1. (WO2018182918) PHASE DETECTOR IN A DELAY LOCKED LOOP

Pub. No.:    WO/2018/182918    International Application No.:    PCT/US2018/020545
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Fri Mar 02 00:59:59 CET 2018
IPC: H03L 7/089
H03L 7/081
Applicants: INTEL CORPORATION
Inventors: WEI, Fangxing
SHI, Dan
ALLEN, Michael
Title: PHASE DETECTOR IN A DELAY LOCKED LOOP
Abstract:
Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.