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1. (WO2018182755) INNOVATIVE WAY TO DESIGN SILICON TO OVERCOME RETICLE LIMIT

Pub. No.:    WO/2018/182755    International Application No.:    PCT/US2017/025663
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Sun Apr 02 01:59:59 CEST 2017
IPC: H01L 25/065
H01L 25/07
H01L 23/532
H01L 23/00
Applicants: INTEL CORPORATION
HOSSAIN, MD Altaf
SOMASEKHAR, Dinesh
SUBBAREDDY, Dheeraj
Inventors: HOSSAIN, MD Altaf
SOMASEKHAR, Dinesh
SUBBAREDDY, Dheeraj
Title: INNOVATIVE WAY TO DESIGN SILICON TO OVERCOME RETICLE LIMIT
Abstract:
Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.