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1. (WO2018182741) TRANSISTORS WITH NON-VERTICAL GATES

Pub. No.:    WO/2018/182741    International Application No.:    PCT/US2017/025610
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Sat Apr 01 01:59:59 CEST 2017
IPC: H01L 29/423
H01L 21/28
H01L 29/66
H01L 29/04
Applicants: INTEL CORPORATION
Inventors: HUANG, Cheng-Ying
MA, Sean, T.
RACHMADY, Willy
DEWEY, Gilbert
METZ, Matthew, V.
KENNEL, Harold, W.
KAVALIEROS, Jack, T.
MURTHY, Anand, S.
GHANI, Tahir
Title: TRANSISTORS WITH NON-VERTICAL GATES
Abstract:
In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having comers and thereby reduce leakage current in the transistor. In one embodiment, the non- vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non- vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.