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1. (WO2018182730) A VERTICAL 1T-1C DRAM ARRAY

Pub. No.:    WO/2018/182730    International Application No.:    PCT/US2017/025551
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Sat Apr 01 01:59:59 CEST 2017
IPC: H01L 27/108
Inventors: PILLARISETTY, Ravi
LE, Van, H.
DEWEY, Gilbert
SHARMA, Abhishek, A.
A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.