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1. (WO2018182724) TECHNIQUE FOR CREATING A SELF-ALIGNED BITLINE IN A VERTICAL FET
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Pub. No.: WO/2018/182724 International Application No.: PCT/US2017/025529
Publication Date: 04.10.2018 International Filing Date: 31.03.2017
IPC:
H01L 27/108 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/66 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
PILLARISETTY, Ravi; US
SHARMA, Abhishek A.; US
LE, Van H.; US
DEWEY, Gilbert; US
RACHMADY, Willy; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) TECHNIQUE FOR CREATING A SELF-ALIGNED BITLINE IN A VERTICAL FET
(FR) TECHNIQUE DE CRÉATION D'UNE LIGNE DE BITS AUTO-ALIGNÉE DANS UN TRANSISTOR À EFFET DE CHAMP VERTICAL
Abstract:
(EN) A transistor array including a plurality of transistors aligned in a row on a substrate, wherein each of the plurality of transistors includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel; and an address line coupled to each of the plurality of transistors and having a width dimension equivalent to a width dimension of the body of each of plurality of transistors. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the transistor bodies; etching the transistor bodies through the masking material to define a plurality of transistors having a width dimension defined by a width dimension of the masking material; and replacing the masking material with an address line material.
(FR) Cette invention concerne un réseau de transistors, comprenant une pluralité de transistors alignés dans une rangée sur un substrat, chacun de la pluralité de transistors comprenant un corps comprenant une première région de diffusion et une seconde région de diffusion sur la première région de diffusion et séparées par un canal ; et une ligne d'adresse couplée à chacun de la pluralité de transistors et ayant une dimension de la largeur équivalente à une dimension de la largeur du corps de chacun de la pluralité de transistors. L'invention concerne en outre un procédé de formation d'un circuit intégré, comprenant : la formation de corps de transistor en une pluralité de rangées sur un substrat ; la formation d'un matériau de masquage sous la forme d'une pluralité de rangées à travers les corps de transistor ; la gravure des corps de transistor à travers le matériau de masquage pour définir une pluralité de transistors ayant une dimension de la largeur définie par une dimension de la largeur du matériau de masquage ; et le remplacement du matériau de masquage par un matériau de ligne d'adresse.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)