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1. (WO2018182720) TECHNIQUE FOR CONTACT FORMATION IN A VERTICAL TRANSISTOR

Pub. No.:    WO/2018/182720    International Application No.:    PCT/US2017/025517
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Sat Apr 01 01:59:59 CEST 2017
IPC: H01L 29/78
H01L 29/08
H01L 27/108
Applicants: INTEL CORPORATION
Inventors: PILLARISETTY, Ravi
SHARMA, Abhishek A.
LE, Van H.
DEWEY, Gilbert
RACHMADY, Willy
Title: TECHNIQUE FOR CONTACT FORMATION IN A VERTICAL TRANSISTOR
Abstract:
A transistor apparatus including a body disposed on a substrate, the body including a first diffusion region and a second diffusion region on the first diffusion region, wherein the first diffusion region and the second diffusion region are separated by a channel; and a gate stack coupled to the channel and offset from the body, the gate stack including a gate dielectric and a gate electrode. A method of forming an integrated circuit including forming a layer of a diffusion material on a substrate; forming a layer of a channel material on the diffusion material; patterning the layer of the channel material and the layer of the diffusion material into a fin including a first diffusion region of the diffusion material and a channel of the channel material; forming a gate stack on the channel; and forming a second diffusion region on the channel.