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1. (WO2018182689) VERTICAL SHARED GATE THIN-FILM TRANSISTOR-BASED CHARGE STORAGE MEMORY

Pub. No.:    WO/2018/182689    International Application No.:    PCT/US2017/025391
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Sat Apr 01 01:59:59 CEST 2017
IPC: H01L 27/108
H01L 29/786
H01L 27/12
Applicants: INTEL CORPORATION
Inventors: SHARMA, Abhishek Anil
LE, Van H.
DEWEY, Gilbert William
RIOS, Rafael
KAVALIEROS, Jack T.
WANG, Yih
SHIVARAMAN, Shriram
Title: VERTICAL SHARED GATE THIN-FILM TRANSISTOR-BASED CHARGE STORAGE MEMORY
Abstract:
A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.