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1. (WO2018182687) FIELD EFFECT TRANSISTOR STRUCTURES
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Pub. No.: WO/2018/182687 International Application No.: PCT/US2017/025382
Publication Date: 04.10.2018 International Filing Date: 31.03.2017
IPC:
H01L 29/78 (2006.01) ,H01L 29/66 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants: INTEL CORPORATION[US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors: RACHMADY, Willy; US
METZ, Matthew V.; US
DEWEY, Gilbert; US
MA, Sean T.; US
Agent: GRIFFIN, III, Malvern U.; US
CHAN, Christopher J.; US
HANNON, James M.; US
BAKHSH, Umar R.; US
ZOGAIB, Nash M.; US
BRANSON, Joshua W.; US
NARVAEZ, Gustavo A.; US
Priority Data:
Title (EN) FIELD EFFECT TRANSISTOR STRUCTURES
(FR) STRUCTURES DE TRANSISTOR À EFFET DE CHAMP
Abstract:
(EN) Solid-state devices having a semiconductor layer passivating a portion of a carrier transport medium are provided. Processes to form such devices also are provided. The semiconductor layer can be adjacent to a transport electrode of a solid-state device, and can form an interface with a spacer layer that separates a gate electrode and the transport electrode. In some embodiments, the carrier transport medium can be formed from a first III-V semiconductor compound, and the semiconductor layer can be formed from a second III-V semiconductor compound. The energy bandgap of the first III-V semiconductor compound can be less than the energy bandgap of the second III-V semiconductor compound. In addition or in other embodiments, the semiconductor layer can have a substantially uniform thickness in a range from about 1 nm to about 5 nm.
(FR) La présente invention concerne des dispositifs à semi-conducteurs ayant une couche semi-conductrice passivant une partie d'un moyen de transport de support. L'invention concerne également des procédés de formation de tels dispositifs. La couche semi-conductrice peut être adjacente à une électrode de transport d'un dispositif à semi-conducteurs, et peut former une interface avec une couche d'espacement qui sépare une électrode de grille et l'électrode de transport. Dans certains modes de réalisation, le moyen de transport de support peut être formé à partir d'un premier composé semi-conducteur III-V, et la couche semi-conductrice peut être formée à partir d'un second composé semi-conducteur III-V. La bande interdite d'énergie du premier composé semi-conducteur III-V peut être inférieure à la bande interdite d'énergie du second composé semi-conducteur III-V. En outre ou dans d'autres modes de réalisation, la couche semi-conductrice peut avoir une épaisseur sensiblement uniforme dans une plage d'environ 1 nm à environ 5 nm.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)