Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018182643) THREE-DIMENSIONAL DECOUPLING INTEGRATION WITHIN HOLE IN MOTHERBOARD
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/182643 International Application No.: PCT/US2017/025152
Publication Date: 04.10.2018 International Filing Date: 30.03.2017
IPC:
H01L 25/07 (2006.01) ,H01L 25/065 (2006.01) ,H01L 23/48 (2006.01) ,H01L 25/16 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16
the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
GO, Jia Yan; MY
LIM, Min Suet; MY
CHUAH, Tin Poay; MY
LIM, Seok Ling; MY
LOO, Howe Yin; MY
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) THREE-DIMENSIONAL DECOUPLING INTEGRATION WITHIN HOLE IN MOTHERBOARD
(FR) INTÉGRATION DE DÉCOUPLAGE TRIDIMENSIONNEL DANS UN TROU DANS UNE CARTE MÈRE
Abstract:
(EN) Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).
(FR) L'invention concerne des boîtiers de semi-conducteur et un procédé de formation d'un boîtier de semi-conducteur. Le boîtier de semi-conducteur comporte une couche de base montée sur une carte mère. Le boîtier de semi-conducteur comprend également un trou dans la carte mère (HiMB) qui est formé dans la carte mère. Le boîtier de semi-conducteur comprend un ou plusieurs condensateur(s) monté(s) sur un blindage électrique. Le blindage électrique peut être incorporé dans le HiMB de la carte mère. En conséquence, le boîtier de semi-conducteur comporte des condensateurs intégrés verticalement entre le blindage électrique et le HiMB de la carte mère. Le boîtier de semi-conducteur peut également comporter une ou plusieurs paroi(s) latérale(s) de HiMB formée(s) sur le HiMB, chacune des parois comprenant un ou plusieurs trou(s) traversant(s) plaqué(s) (PTH) présentant une couche exposée. Les PTH peuvent être couplés électriquement aux condensateurs lorsque les condensateurs sont intégrés verticalement entre les parois latérales de blindage électrique et les parois latérales des HiMB (c'est-à-dire, des condensateurs tridimensionnels (3D)).
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)