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1. (WO2018182619) CO-INTEGRATING COMPOSITIONALLY DIFFERENT SEMICONDUCTOR MATERIALS USING A COMMON THIN SEED LAYER

Pub. No.:    WO/2018/182619    International Application No.:    PCT/US2017/025018
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Fri Mar 31 01:59:59 CEST 2017
IPC: H01L 27/088
H01L 21/8234
H01L 29/417
H01L 29/10
Applicants: INTEL CORPORATION
Inventors: RACHMADY, Willy
RADOSAVLJEVIC, Marko
LE, Van H.
PILLARISETTY, Ravi
METZ, Matthew V.
AGRAWAL, Ashish
CHU-KUNG, Benjamin
DEWEY, Gilbert
SUNG, Seung Hoon
Title: CO-INTEGRATING COMPOSITIONALLY DIFFERENT SEMICONDUCTOR MATERIALS USING A COMMON THIN SEED LAYER
Abstract:
Techniques are disclosed for monolithically co-integrating compositionally different semiconductor materials using a common thin monocrystalline semiconductor seed layer. In some embodiments, the shared seed layer allows for the overlying compositionally different monocrystalline semiconductor materials to be formed in a defect free or substantially defect free manner. This occurs because the seed layer is sufficiently thin such that it can allow itself to be strained by the growth of overlying monocrystalline semiconductor fin structures, which is referred to as strain transfer or compliant effect. As a result, misfit dislocations that would otherwise form in the overlying monocrystalline semiconductor material of the fins formed on the seed layer may not form at all (or may form at a lower rate/quantity), enabling the monocrystalline semiconductor material fins to be formed in an enhanced quality manner. Non-planar transistor architectures such as FinFET and gate-all-around can be formed using the fins.