Search International and National Patent Collections

1. (WO2018182609) VERTICAL MULTI-GATE THIN FILM TRANSISTORS

Pub. No.:    WO/2018/182609    International Application No.:    PCT/US2017/024969
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Fri Mar 31 01:59:59 CEST 2017
IPC: H01L 29/786
H01L 29/66
H01L 27/108
H01L 27/12
Applicants: INTEL CORPORATION
Inventors: WANG, Yih
SHARMA, Abhishek
MA, Sean
LE, Van
Title: VERTICAL MULTI-GATE THIN FILM TRANSISTORS
Abstract:
Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).