WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Options
Query Language
Stem
Sort by:
List Length
Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018181417) POWER MODULE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/181417 International Application No.: PCT/JP2018/012634
Publication Date: 04.10.2018 International Filing Date: 28.03.2018
IPC:
H01L 23/36 (2006.01) ,H01L 21/52 (2006.01) ,H01L 21/60 (2006.01) ,H01L 23/12 (2006.01) ,H01L 29/12 (2006.01) ,H01L 29/739 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52
Mounting semiconductor bodies in containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants: ROHM CO., LTD.[JP/JP]; 21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto-shi, Kyoto 6158585, JP
Inventors: HATANO Maiko; JP
OTSUKA Takukazu; JP
Agent: MIYOSHI Hidekazu; JP
TERAYAMA Keishin; JP
Priority Data:
2017-07188031.03.2017JP
Title (EN) POWER MODULE AND METHOD FOR MANUFACTURING SAME
(FR) MODULE D'ALIMENTATION ET SON PROCÉDÉ DE FABRICATION
(JA) パワーモジュールおよびその製造方法
Abstract:
(EN) A power module (1) is provided with: a flat-plate-shaped thick copper substrate (2); a conductive stress relaxation metal layer (24U) disposed on the thick copper substrate (2); a semiconductor device (22) disposed on the stress relaxation metal layer (24U); and a plated layer (30) disposed on the stress relaxation metal layer (24U). The semiconductor device (22) is joined to the stress relaxation metal layer (24U) with the plated layer (30) interposed therebetween. The thick copper substrate (2) is provided with: a first thick copper layer (14); and a second thick copper layer (18) disposed on the first thick copper layer (14). The stress relaxation metal layer (24U) is disposed on the second thick copper layer (18). A part of the semiconductor device (22) is sunk into the stress relaxation metal layer (24U) and is fixed thereto. The joint surfaces of the semiconductor device (22) and the stress relaxation metal layer (24U) are integrated via diffusion bonding or solid-phase diffusion bonding. Thus provided is a power module in which the reliability of a joint is enhanced without increasing thermal resistance.
(FR) La présente invention concerne un module d'alimentation qui est pourvu : d'un substrat en cuivre épais en forme de plaque plate (2) ; d'une couche métallique de relaxation de contrainte conductrice (24U) disposée sur le substrat en cuivre épais (2) ; d'un dispositif à semi-conducteurs (22) disposé sur la couche métallique de relaxation de contrainte (24U) ; et d'une couche plaquée (30) disposée sur la couche métallique de relaxation de contrainte (24U). Le dispositif à semi-conducteurs (22) est relié à la couche métallique de relaxation de contrainte (24U), la couche plaquée (30) étant interposée entre eux. Le substrat en cuivre épais (2) est pourvu : d'une première couche en cuivre épaisse (14) ; et d'une seconde couche en cuivre épaisse (18) disposée sur la première couche en cuivre épaisse (14). La couche métallique de relaxation de contrainte (24U) est disposée sur la seconde couche en cuivre épaisse (18). Une partie du dispositif à semi-conducteurs (22) est enfoncée dans la couche métallique de relaxation de contrainte (24U) et y est fixée. Les surfaces de joint du dispositif à semi-conducteurs (22) et de la couche métallique de relaxation de contrainte (24U) sont intégrées par liaison par diffusion ou liaison par diffusion en phase solide. Ainsi, l'invention concerne un module d'alimentation dans lequel la fiabilité d'un joint est améliorée sans augmenter la résistance thermique.
(JA) パワーモジュール(1)は、平板状の厚銅基板(2)と、厚銅基板(2)上に配置された導電性の応力緩和金属層(24U)と、応力緩和金属層(24U)上に配置された半導体デバイス(22)と、応力緩和金属層(24U)上に配置されたメッキ層(30)を備え、半導体デバイス(22)は、メッキ層(30)を介して、応力緩和金属層(24U)と接合している。厚銅基板(2)は、第1厚銅層(14)と、第1厚銅層(14)上に配置された第2厚銅層(18)とを備え、応力緩和金属層(24U)は、第2厚銅層(18)上に配置される。半導体デバイス(22)の一部は、応力緩和金属層(24U)に食い込んで固着している。半導体デバイス(22)と応力緩和金属層(24U)との接合面は、拡散接合若しくは固相拡散接合により一体化されている。熱抵抗を増加させることなく、接合の信頼性の向上が可能なパワーモジュールを提供する。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)