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1. (WO2018181264) ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE HAVING SAME
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/181264 International Application No.: PCT/JP2018/012334
Publication Date: 04.10.2018 International Filing Date: 27.03.2018
IPC:
G02F 1/1368 (2006.01) ,G09F 9/30 (2006.01) ,G09G 3/20 (2006.01) ,G09G 3/36 (2006.01) ,H01L 29/786 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1 Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
西山 隆之 NISHIYAMA Takayuki; --
米林 諒 YONEBAYASHI Ryo; --
田中 耕平 TANAKA Kohhei; --
Agent:
川上 桂子 KAWAKAMI Keiko; JP
松山 隆夫 MATSUYAMA Takao; JP
Priority Data:
2017-06446029.03.2017JP
Title (EN) ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE HAVING SAME
(FR) SUBSTRAT MATRICIEL ACTIF ET DISPOSITIF D'AFFICHAGE LE COMPRENANT
(JA) アクティブマトリクス基板、及びそれを備えた表示装置
Abstract:
(EN) Provided is a technique making it possible to easily arrange a driving circuit for driving a gate line in a pixel and reduce display defects in the form of vertical stripes. This active matrix substrate includes a pixel electrode 141 and a pixel switching element 10 connected to a gate line 13, a source line 15, and the pixel electrode 141 in each pixel PIX. A driving circuit element 110 of a driving circuit for driving the gate line 13 is arranged in a light shielding region BM of some of the pixels PIX in a display region. An interval between the pixel switching elements 10 in a row of the pixels where the driving circuit element 110 is arranged is not uniform, and the drains of the pixel switching elements 10 in the same row are in the same direction with respect to the source lines connected thereto.
(FR) L'invention concerne une technique permettant d'agencer facilement un circuit d'attaque pour l'attaque d'une ligne de grille dans un pixel et pour la réduction des défauts d'affichage sous la forme de bandes verticales. Ledit substrat matriciel actif comprend une électrode (141) de pixel et un élément de commutation (10) de pixels connecté à une ligne de grille (13), à une ligne de source (15) et à l'électrode (141) de pixel dans chaque pixel PIX. Un élément (110) de circuit d'attaque d'un circuit d'attaque pour l'attaque de la ligne de grille (13) est agencé dans une région de protection contre la lumière BM de certains des pixels PIX dans une région d'affichage. Un intervalle entre les éléments de commutation (10) de pixels dans une rangée des pixels où l'élément (110) de circuit d'attaque est agencé, n'est pas uniforme et les drains des éléments de commutation (10) de pixels dans la même rangée sont dans la même direction par rapport aux lignes de source qui y sont connectées.
(JA) ゲート線を駆動する駆動回路を画素内に配置しやすく、且つ縦縞状の表示不良を軽減し得る技術を提供する。アクティブマトリクス基板は、画素PIXに、画素電極141と、ゲート線13とソース線15と画素電極141とに接続された画素用スイッチング素子10とを備える。ゲート線13を駆動する駆動回路の駆動回路用素子110は、表示領域における一部の画素PIXの遮光領域BMに配置される。駆動回路用素子110の設置画素の行における画素用スイッチング素子10の間隔は均一でなく、同じ行の画素用スイッチング素子10のドレインは、接続されるソース線に対して同じ方向にある。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)