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1. (WO2018180842) TFT SUBSTRATE, TFT SUBSTRATE PRODUCTION METHOD, AND DISPLAY DEVICE
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/180842 International Application No.: PCT/JP2018/011294
Publication Date: 04.10.2018 International Filing Date: 22.03.2018
IPC:
G09F 9/30 (2006.01) ,G02F 1/1343 (2006.01) ,G02F 1/1368 (2006.01) ,H01L 27/32 (2006.01) ,H01L 29/786 (2006.01) ,H01L 51/50 (2006.01) ,H05B 33/02 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
1343
Electrodes
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
28
including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
32
with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
50
specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
B
ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
33
Electroluminescent light sources
02
Details
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
岡部 達 OKABE, Tohru; --
錦 博彦 NISHIKI, Hirohiko; --
家根田 剛士 YANEDA, Takeshi; --
Agent:
特許業務法人HARAKENZO WORLD PATENT & TRADEMARK HARAKENZO WORLD PATENT & TRADEMARK; 大阪府大阪市北区天神橋2丁目北2番6号 大和南森町ビル Daiwa Minamimorimachi Building, 2-6, Tenjinbashi 2-chome Kita, Kita-ku, Osaka-shi, Osaka 5300041, JP
Priority Data:
2017-06535529.03.2017JP
Title (EN) TFT SUBSTRATE, TFT SUBSTRATE PRODUCTION METHOD, AND DISPLAY DEVICE
(FR) SUBSTRAT TFT, PROCÉDÉ DE PRODUCTION DE SUBSTRAT TFT, ET DISPOSITIF D'AFFICHAGE
(JA) TFT基板、TFT基板の製造方法、表示装置
Abstract:
(EN) The present invention achieves stable connection, in a TFT substrate including a semiconductor film in each of a lower layer part and an upper layer part thereof, between a conductor in the lower layer part and a conductor in the upper layer part. The substrate is provided thereon with: a first semiconductor film (6) that functions as a channel for TFT; a first conductor (M1) that is disposed in a layer above the first semiconductor film; an interlayer insulating film (18) that is disposed in a layer above the first conductor; a second semiconductor film (26) that is disposed in a layer above the interlayer insulating film; a second conductor (J2) that is disposed in a layer above the second semiconductor film; an organic insulating film (32) that is disposed in a layer above the second conductor; a third conductor (M3) that is disposed in a layer above the organic insulating film; and a contact hole (CH) that extends through a through-hole (H32) in the organic insulating film and a through-hole (H18) in the interlayer insulating film and reaches the first conductor, wherein the second conductor (J2) and the third conductor (M3) are formed so as to overlap the opening plane (K) of the contact hole, and the third conductor (M3) is in contact with the first conductor (M1) and the second conductor (J2).
(FR) La présente invention réalise une connexion stable, dans un substrat TFT comprenant un film semi-conducteur dans une partie de couche inférieure et une partie de couche supérieure de ce dernier, entre un conducteur dans la partie de couche inférieure et un conducteur dans la partie de couche supérieure. Le substrat est pourvu : d'un premier film semi-conducteur (6) qui fonctionne comme un canal pour TFT ; d'un premier conducteur (M1) qui est disposé dans une couche au-dessus du premier film semi-conducteur ; un film isolant intercouche (18) qui est disposé dans une couche au-dessus du premier conducteur ; un second film semi-conducteur (26) qui est disposé dans une couche au-dessus du film isolant intercouche ; un second conducteur (J2) qui est disposé dans une couche au-dessus du second film semi-conducteur ; un film isolant organique (32) qui est disposé dans une couche au-dessus du second conducteur ; un troisième conducteur (M3) qui est disposé dans une couche au-dessus du film isolant organique ; et un trou de contact (CH) qui s'étend à travers un trou traversant (H32) dans le film isolant organique et un trou traversant (H18) dans le film isolant intercouche et qui atteint le premier conducteur, le second conducteur (J2) et le troisième conducteur (M3) étant formés de manière à chevaucher le plan d'ouverture (K) du trou de contact, et le troisième conducteur (M3) est en contact avec le premier conducteur (M1) et le second conducteur (J2).
(JA) 下層部および上層部それぞれに半導体膜を含むTFT基板において、下層部の導電体と上層部の導電体との安定的な接続を図る。基板上に、TFTのチャネルとして機能する第1半導体膜(6)と、第1半導体膜よりも上層の第1導電体(M1)と、第1導電体よりも上層の層間絶縁膜(18)と、層間絶縁膜よりも上層の第2半導体膜(26)と、第2半導体膜よりも上層の第2導電体(J2)と、第2導電体よりも上層の有機絶縁膜(32)と、有機絶縁膜よりも上層の第3導電体(M3)と、有機絶縁膜のスルーホール(H32)および層間絶縁膜のスルーホール(H18)を通って第1導電体に到るコンタクトホール(CH)とを備え、第2導電体(J2)および第3導電体(M3)がコンタクトホールの開口面(K)と重なるように形成され、第3導電体(M3)が第1導電体(M1)および第2導電体(J2)と接触する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)