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1. (WO2018180536) PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, PROGRAMMING METHOD THEREFOR AND PROGRAM THEREFOR
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/180536 International Application No.: PCT/JP2018/010177
Publication Date: 04.10.2018 International Filing Date: 15.03.2018
IPC:
H03K 19/177 (2006.01) ,H01L 21/82 (2006.01) ,H01L 21/822 (2006.01) ,H01L 21/8239 (2006.01) ,H01L 27/04 (2006.01) ,H01L 27/105 (2006.01) ,H01L 45/00 (2006.01) ,H01L 49/00 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02
using specified components
173
using elementary logic circuits as components
177
arranged in matrix form
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
日本電気株式会社 NEC CORPORATION [JP/JP]; 東京都港区芝五丁目7番1号 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001, JP
Inventors:
多田 あゆ香 TADA Ayuka; JP
阪本 利司 SAKAMOTO Toshitsugu; JP
宮村 信 MIYAMURA Makoto; JP
辻 幸秀 TSUJI Yukihide; JP
根橋 竜介 NEBASHI Ryusuke; JP
白 旭 BAI Xu; JP
Agent:
下坂 直樹 SHIMOSAKA Naoki; JP
Priority Data:
2017-06286828.03.2017JP
Title (EN) PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, PROGRAMMING METHOD THEREFOR AND PROGRAM THEREFOR
(FR) CIRCUIT INTÉGRÉ LOGIQUE PROGRAMMABLE, SON PROCÉDÉ DE PROGRAMMATION ET PROGRAMME ASSOCIÉ
(JA) プログラマブル論理集積回路とそのプログラミング方法及びそのプログラム
Abstract:
(EN) The purpose of the present invention is to provide a circuit capable of reducing leakage power in a programmable logic circuit using resistance change elements. To this end, the present invention is a programmable logic integrated circuit comprising a switch matrix provided with, as a switch element, a plurality of first resistance change elements connected to an input line and an output line, wherein a buffer is connected to the output line, the programmable logic integrated circuit being characterized in that power is not supplied to the buffer that is connected to the output line and does not contribute to an operation of a desired logic circuit, the operation being caused when the logic circuit has been programmed.
(FR) L'objet de la présente invention est de fournir un circuit susceptible de réduire la puissance de fuite dans un circuit logique programmable à l'aide d'éléments de changement de résistance. À cet effet, la présente invention est un circuit intégré logique programmable comprenant une matrice de commutation pourvue, en tant qu'élément de commutation, d'une pluralité de premiers éléments de changement de résistance connectés à une ligne d'entrée et à une ligne de sortie, un tampon étant connecté à la ligne de sortie, le circuit intégré logique programmable étant caractérisé en ce que la puissance n'est pas fournie au tampon qui est connecté à la ligne de sortie et ne contribue pas à un fonctionnement d'un circuit logique souhaité, le fonctionnement étant provoqué lorsque le circuit logique a été programmé.
(JA) 本発明の目的は、抵抗変化素子を用いたプログラマブル論理回路にて、リーク電力を抑制することのできる回路を提供することである。そのために本発明は、入力線と出力線に接続された複数の第1の抵抗変化素子をスイッチ素子として備えたスイッチマトリクスを有し、前記出力線にバッファが接続されたプログラマブル論理集積回路であって、所望の論理回路をプログラムした際に生じる、前記論理回路の動作には寄与しない前記出力線に接続されている前記バッファには電源を供給しないことを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)