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1. (WO2018180536) PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, PROGRAMMING METHOD THEREFOR AND PROGRAM THEREFOR

Pub. No.:    WO/2018/180536    International Application No.:    PCT/JP2018/010177
Publication Date: Fri Oct 05 01:59:59 CEST 2018 International Filing Date: Fri Mar 16 00:59:59 CET 2018
IPC: H03K 19/177
H01L 21/82
H01L 21/822
H01L 21/8239
H01L 27/04
H01L 27/105
H01L 45/00
H01L 49/00
Applicants: NEC CORPORATION
日本電気株式会社
Inventors: TADA Ayuka
多田 あゆ香
SAKAMOTO Toshitsugu
阪本 利司
MIYAMURA Makoto
宮村 信
TSUJI Yukihide
辻 幸秀
NEBASHI Ryusuke
根橋 竜介
BAI Xu
白 旭
Title: PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, PROGRAMMING METHOD THEREFOR AND PROGRAM THEREFOR
Abstract:
The purpose of the present invention is to provide a circuit capable of reducing leakage power in a programmable logic circuit using resistance change elements. To this end, the present invention is a programmable logic integrated circuit comprising a switch matrix provided with, as a switch element, a plurality of first resistance change elements connected to an input line and an output line, wherein a buffer is connected to the output line, the programmable logic integrated circuit being characterized in that power is not supplied to the buffer that is connected to the output line and does not contribute to an operation of a desired logic circuit, the operation being caused when the logic circuit has been programmed.